Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: Disclosed is a method of manufacturing an a-IGZO TFT-based transient semiconductor. The method includes (a) stacking a thermal oxide layer on a silicon substrate and depositing a nickel thin layer; (b) forming a PECVD layer on the nickel thin layer; (c) patterning the PECVD layer after setting a gate area and depositing a metallic layer; (d) lifting off the metallic layer to form a gage metallic thin layer and depositing a gage insulating layer on the gate metallic thin layer; (e) depositing an a-IGZO layer on the gate insulating layer; (f) etching an active area and the gate insulating layer; (g) forming a source electrode and a drain electrode and attaching a thermal release tape on the source electrode and the drain electrode; (h) delaminating the nickel thin layer; (i) performing transcription on a polyvinyl alcohol thin layer after etching the nickel thin layer; and (j) detaching the tape.

Abstract: Provided is a field-effect transistor (FET) that achieves compatibility between a higher current density and lower contact resistance and exhibits excellent properties, and a method for producing the FET. The FET includes: a channel layer above a substrate; an InAlN layer above the channel layer; an InxAlyGa1-(x+y)N layer on the InAlN layer, where 0<x<1, 0<y<1, and x+y<1; and a source electrode and a drain electrode formed on the InxAlyGa1-(x+y)N layer.

Abstract: In a MOSFET, the lead parts of gate lead wiring that lead out a gate electrode on the periphery of a substrate constitute a non-operative region where it is impossible to dispose a MOSFET transistor cell (C) that will function as efficiently as inside an element region. If the gate lead wiring is disposed along the four edges of a chip, for example, the area of the non-operative region increases, limiting the extent to which the surface area of the element region can be enlarged and the chip surface area reduced. In the present invention, gate lead wiring and a conductor, which is connected to the gate lead wiring and a protection diode, are disposed in a non-curved, linear configuration along one edge of a chip. In addition, a first gate electrode layer that extends superimposed on the gate lead wiring and the conductor, and connects the gate lead wiring and the conductor to the protection diode, has no more than one curved part.

Abstract: A semiconductor device having a horizontal gate all around structure is provided. The semiconductor device includes a substrate and a fin. The fin is disposed on the substrate, and includes an anti-punch through (APT) layer formed of a material at a dose of about 1E18 atoms/cm2 to about 1E19 atoms/cm2, and a barrier layer formed above the APT layer. A method of forming a semiconductor device having a horizontal gate all around structure is also provided.

Abstract: Provided is a method for manufacturing a microchannel resonator capable of measuring a mass and characteristics of an object using a principle in which a resonance frequency is changed according to a mass of a moving material, the method including: providing a silicon substrate; forming a cavity channel inside the silicon substrate; forming a hollow silicon oxide structure on the inner wall surface of the cavity channel by oxidizing the inner wall surface of the cavity channel; and partially removing the periphery of the hollow silicon oxide structure such that the hollow silicon oxide structure can resonate with respect to the silicon substrate.

Abstract: Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.

Abstract: A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of ±10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>±20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

Abstract: The present invention relates to the use of light-converting, colloidal, doped semiconductor nanocrystals to provide a new generation of high performance, low cost monochromatic and white light sources based on LEDs.

Abstract: A method of making a CZTS/inorganic thin-film tandem solar cell including depositing a textured buffer layer on a substrate, depositing a metal-inorganic film from a eutectic alloy on the buffer layer, and depositing additional elements in CZTS forming a CZTS layer based on the metal from the metal-inorganic film, the metal being incorporated into the CZTS film.

Abstract: According to the present invention, when a film is formed on a substrate, a film-forming rate or film quality is stabilized. There is provided a method of manufacturing a semiconductor device, including: (a) forming a film on a substrate by supplying at least a gas including hydroxyl group to the substrate in a process chamber while maintaining a temperature of an inside of the process chamber at a first temperature; (b) changing the temperature of the inside of the process chamber from the first temperature to a second temperature higher than the first temperature; and (c) maintaining the temperature of the inside of the process chamber at the second temperature at least in a state that the substrate is not in the process chamber.

Abstract: A seed crystal substrate 8 includes a base body 1 and a plurality of rows of stripe-shaped seed crystal layers 3 formed on the base body 1. An upper face 3a of the seed crystal layer 3 is (11-22) plane, a groove 4 is formed between the adjacent seed crystal layers 3, and a longitudinal direction of the groove 4 is a direction in which a c-axis of a crystal forming the seed crystal layer is projected on the upper face. A nitride of a group 13 element is formed on the seed crystal substrate.

Abstract: To manufacture a semiconductor device using an oxide semiconductor with high reliability and less variation in electrical characteristics, objects are to provide a method for manufacturing a semiconductor device with which an oxide semiconductor film with a fairly uniform thickness is formed, a manufacturing apparatus, and a method for manufacturing a semiconductor device with the manufacturing apparatus. In order to form an oxide semiconductor film with a fairly uniform thickness with use of a sputtering apparatus, an oxide semiconductor film the thickness uniformity of which is less than ±3%, preferably less than or equal to ±2% is formed by using a manufacturing apparatus in which a deposition chamber is set to have a reduced pressure atmosphere, preferably, to have a high degree of vacuum and power is adjusted to be applied uniformly to the entire surface of a substrate during film deposition.

Abstract: A processing chamber for processing a substrate is disclosed herein. In one embodiment, the processing chamber includes a liner assembly disposed within an interior volume of the processing chamber, and a C-channel disposed in an interior volume of the chamber, circumscribing the liner assembly. In another embodiment, a process kit disposed in the interior volume of the processing chamber is disclosed herein. The process kit includes a liner assembly, a C-channel, and an isolator disposed in the interior volume. The C-channel and the isolator circumscribe the liner assembly. A method for depositing a silicon based material on a substrate by flowing a precursor gas into a processing chamber is also described herein.

Abstract: Methods and systems for direct atomic layer etching and deposition on or in a substrate using charged particle beams. Electrostatically-deflected charged particle beam columns can be targeted in direct dependence on the design layout database to perform atomic layer etch and atomic layer deposition, expressing pattern with selected 3D-structure. Reducing the number of process steps in patterned atomic layer etch and deposition reduces manufacturing cycle time and increases yield by lowering the probability of defect introduction. Local gas and photon injectors and detectors are local to corresponding columns, and support superior, highly-configurable process execution and control.

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

Abstract: A method for producing an organic semiconductor device (110) having at least one organic semiconducting material (122) and at least two electrodes (114) adapted to support an electric charge carrier transport through the organic semiconducting material (122) is disclosed. The organic semiconducting material (122) intrinsically has ambipolar semiconducting properties. The method comprises at least one step of generating at least one intermediate layer (120) which at least partially is interposed between the organic semiconducting material (122) and at least one of the electrodes (114) of the organic semiconductor device (110). The intermediate layer (120) comprises at least one thiol compound having the general formula HS—R, wherein R is an organic residue. The thiol compound has an electric dipole moment pointing away from the SH-group of the thiol compound. The electric dipole moment has at least the same magnitude as the electric dipole moment in 4-Phenylthiophenol.

Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.

Abstract: Structures for spacers of a field-effect transistor and methods for forming such spacers. A mask layer has a feature separated from a vertical sidewall of a first gate structure by a space of predetermined width that exposes a top surface of a semiconductor body. A spacer is formed adjacent to the vertical sidewall of the first gate structure. The spacer has a first section in the space and a second section. The first section of the spacer is located vertically between the second section of the spacer and the top surface of the semiconductor body. The first section of the spacer extends through the space to the top surface of the semiconductor body, and the first section of the spacer fully fills the space.

Abstract: An integrated circuit includes stacked benzocyclobutene layers and a circuit geometry comprising conductive electric traces and interconnects on and/or extending through the BCB layers. A first said BCB layer formed and partially cured state. A top surface masked with photoresist, and after exposure, etched selectively form through vias at locations corresponding to conductive interconnects of the circuit geometry associated with said first BCB layer. A further mask coating is applied and after exposure, conductive metal is deposited to infill vias and form the electric traces of the circuit geometry. Subsequent BCB layers are then likewise formed, etched masked and coated in the same manner.