Abstract: The organic electroluminescence element in accordance with the present invention includes: a light-emitting layer; a first electrode layer disposed on a first surface in a thickness direction of the light-emitting layer; a second electrode layer disposed on a second surface in the thickness direction of the light-emitting layer; and an electrically conductive layer. The light-emitting layer is configured to emit light when a predetermined voltage is applied between the first electrode layer and the second electrode layer. The second electrode layer includes an electrode part covering the second surface and an opening part formed in the electrode part to expose the second surface. The electrically conductive layer is configured to allow the light to pass therethrough, and is formed on an exposed region of the second surface exposed through the opening part in such a way as to be electrically connected to the electrode part and the light-emitting layer.

Abstract: Provided are a semiconductor device in which abrasive grain marks are formed in a surface of a semiconductor substrate, a dopant diffusion region has a portion extending in a direction which forms an angle included in a range of ?5° to +5° with a direction in which the abrasive grain marks extend, and the dopant diffusion region is formed by diffusing a dopant from a doping paste placed on one surface of the semiconductor substrate; and a method for manufacturing the semiconductor device.

Abstract: A no-lead type semiconductor package has a mold cap that forms a mold body. The corners of the mold body are reinforced with mold columns such that the corners have rounded protrusions and do not form 90° angles. The mold columns prevent the corner pads from peeling.

Abstract: A first fin field effect transistor and a second fin field effect transistor are formed on an insulator layer overlying a semiconductor material layer. A first pair of trenches is formed through the insulator layer in regions in which a source region and a drain region of the first fin field effect transistor is to be formed. A second pair of trenches is formed partly into the insulator layer without extending to the top surface of the semiconductor material layer. The source region and the drain region of the first field effect transistor can be epitaxial stressor material portions that are anchored to, and epitaxially aligned to, the semiconductor material layer and apply stress to the channel of the first field effect transistor to enhance performance. The insulator layer provides electrical isolation from the semiconductor material layer to the second field effect transistor.

Abstract: A method for making an electronic device, such as a MOS transistor, including the steps of forming a plurality of semiconductor islands on an electrically functional substrate, printing a first dielectric layer on or over a first subset of the semiconductor islands and optionally a second dielectric layer on or over a second subset of the semiconductor islands, and annealing. The first dielectric layer contains a first dopant, and the (optional) second dielectric layer contains a second dopant different from the first dopant. The dielectric layer(s), semiconductor islands and substrate are annealed sufficiently to diffuse the first dopant into the first subset of semiconductor islands and, when present, the second dopant into the second subset of semiconductor islands.

Abstract: An organic light emitting display device includes first and second electrodes facing each other on a substrate, at least one emission layer formed between the first and second electrodes, a hole transport layer formed between the first electrode and the emission layer, and an electron transport layer formed between the second electrode and the emission layer, wherein the emission layer includes a first emission mixed layer formed on the hole transport layer, the first emission mixed layer including a first hole-type host and a first phosphorescent dopant, and a second emission mixed layer formed between the first emission mixed layer and the electron transport layer, the second emission mixed layer including a first electron-type host and a second phosphorescent dopant.

Abstract: A memristor including a dopant source is disclosed. The structure includes an electrode, a conductive alloy including a conducting material, a dopant source material, and a dopant, and a switching layer positioned between the electrode and the conductive alloy, wherein the switching layer includes an electronically semiconducting or nominally insulating and weak ionic switching material. A method for fabricating the memristor including a dopant source is also disclosed.

Abstract: Atomic layer deposition processes for forming germanium oxide thin films are provided. In some embodiments the ALD processes can include the following: contacting the substrate with a vapor phase tetravalent Ge precursor such that at most a molecular monolayer of the Ge precursor is formed on the substrate surface; removing excess Ge precursor and reaction by products, if any; contacting the substrate with a vapor phase oxygen precursor that reacts with the Ge precursor on the substrate surface; removing excess oxygen precursor and any gaseous by-products, and repeating the contacting and removing steps until a germanium oxide thin film of the desired thickness has been formed.

Abstract: Disclosed herein are a power module package and a method for manufacturing the same. According to a preferred embodiment of the present invention, a power module package includes: a metal substrate having an insulating layer and a circuit pattern formed on one surface thereof; at least one first electronic device mounted on the circuit pattern; a lead frame disposed around the metal substrate; a molding area enclosing the metal substrate, the first electronic device, and a portion of the lead frame; and a heat sink including a connection part contacting the insulating layer and a body part disposed on a surface opposite to the first electronic device and including one surface bonded to the connection part and the other surface exposed from an upper surface of the molding area.

Abstract: In one embodiment, a method includes depositing a chalcogenide precursor layer onto a substrate, introducing a cover into proximity with the precursor layer, and annealing the precursor layer in proximity with of the cover, where the annealing is performed in a constrained volume, and where the presence of the cover reduces decomposition of volatile species from the precursor layer during annealing.

Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.

Abstract: The embodiments of the present invention relate to a light emitting diode and manufacturing method thereof. The electroluminescent layer of the light-emitting diode is formed of graphene/compound semiconductor quantum dot composites.

Abstract: A semiconductor device may include a voltage supply unit suitable for supplying a voltage, a first conductive line coupled to the voltage supply unit, a second conductive line formed over the first conductive line, a voltage contact plug formed over the second conductive line, a voltage transmission line formed over the voltage contact plug, and a switching element suitable for switching the voltage transferred from the voltage transmission line.

Abstract: In a semiconductor device having a vertical semiconductor element configured to pass an electric current between an upper electrode and a lower electrode, a field stop layer includes a phosphorus/arsenic layer doped with phosphorus or arsenic and a proton layer doped with proton. The phosphorus/arsenic layer is formed from a back side of a semiconductor substrate to a predetermined depth. The proton layer is deeper than the phosphorus/arsenic layer. An impurity concentration of the proton layer peaks inside the phosphorus/arsenic layer and gradually, continuously decreases at a depth greater than the phosphorus/arsenic layer.

Abstract: The light-emitting device of the disclosure includes at least one LED chip and a mounting substrate. The mounting substrate includes: a ceramic substrate; a reflection layer situated on a second surface on the opposite side of the ceramic substrate from a first surface; and a gas barrier layer covering the reflection layer. The LED chip is bonded to the first surface of the ceramic substrate. The ceramic substrate has light diffusion and transmissive properties and has a plan size larger than a plan size of the LED chip. The reflection layer has a plan size smaller than a plan size of the ceramic substrate and is formed so as to cover an area larger than a projected area of the LED chip on the second surface of the ceramic substrate.

Abstract: There is provided a fabrication technique of a MOS structure that has a small EOT without increasing the interface trap density. More specifically, provided is a method of producing a semiconductor wafer that includes a semiconductor crystal layer, an interlayer made of an oxide, nitride, or oxynitride of a semiconductor crystal constituting the semiconductor crystal layer, and a first insulating layer made of an oxide and in which the semiconductor crystal layer, the interlayer, and the first insulating layer are arranged in the stated order. The method includes (a) forming the first insulating layer on an original semiconductor crystal layer, and (b) exposing a surface of the first insulating layer with a nitrogen plasma to nitride, oxidize, or oxynitride a part of the original semiconductor crystal layer, thereby forming the interlayer, together with the semiconductor crystal layer that is the rest of the original semiconductor crystal layer.

Abstract: Asymmetric styrene derivatives having carbazole and aniline are provided with main BCzVBi structure but impair the symmetry of BCzVBi so as to increase the solubility and applicability in OLED solution process. An OLED device using the asymmetric styrene derivatives is also herein disclosed.

Abstract: A MEMS device and a forming method thereof are provided. The MEMS device includes a semiconductor substrate with a well region formed therein. A source region, a drain region and a channel region are formed in the well region. The source region and the drain region are covered by an isolating layer, and the channel region is covered by a gate dielectric layer. The device further includes a gate electrode layer which is disposed above the gate dielectric layer, with a gap disposed therebetween. The width of the gap corresponds to the width of the channel region. The MEMS can work well at high voltages with less leakage current.

Abstract: Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

Abstract: An organic electroluminescent element in accordance with the present invention includes: a transparent electrode; a blue light-emitting layer containing a blue light-emitting material having a maximum emission wavelength 460 nm or less; a first green light-emitting layer containing a first green light-emitting material having a maximum emission wavelength in the spectrum between 460 nm and 610 nm; a red light-emitting layer containing a red light-emitting material having a maximum emission wavelength of 610 nm or more; a second green light-emitting layer containing a second green light-emitting material having a maximum emission wavelength in the spectrum between 460 nm and 610 nm; and a reflecting electrode. The maximum emission wavelength of the first green light-emitting material is located on a short wavelength side of the spectrum. The maximum emission wavelength of the second green light-emitting material is located on a long wavelength side of the spectrum.