Abstract: A digital circuit configured to spread a clock train spectrum includes a clock configured to generate the clock train, and a variable divider configured to divide the frequency of the clock train by a temporally-varying-divider value to modulate the clock train and generate a dithered clock train. The circuit further includes a first accumulator configured to accumulate the dithered clock train to generate a frequency modulation waveform, and a second accumulator configured accumulate the frequency modulated waveform to generate a phase modulation signal. The circuit further includes a phase-value calculator configured to calculate the temporally-varying divider value based on the phase modulation signal; and a closed-loop control circuit configured to track and filter the modulation of the dithered clock train to generate a second clock train that is the spread spectrum of the first mentioned clock train.

Abstract: The present invention involves a method and system for transmitting two levels of data in a hierarchical transmission schema. A first modulated signal is generated based on first input. A second modulation signal is generated based on a second input that has a data rate that is a fraction of the data rate of the first modulated signal. The second modulation signal has known instances where the second modulation signal has no energy. In a system where the first modulation is quadrature phase shift keying (QPSK), the second modulation signal can be a secondary phase offset. A receiver in the system that has a priori knowledge about the timing relationship between the first data signal and the instances when the second data signal is present will be able to detect both data signals optimally.

Abstract: A digitally-implemented pulse width modulation (PWM) signal generator forms the PWM pulse width as a rational number based on full cycles of a PWM reference clock, and offers a very high effective resolution of the PWM pulse signal that is compatible with multiphase DC-DC converters. Being totally digital allows digital error accumulation and correction to occur at the point of origin of the PWM signal, well upstream of the relatively slow voltage control feedback loop. Quantization errors are corrected before they can accumulate in the converter's DC output voltage.

Abstract: In the invention, it becomes possible to extract all clock information data processing data by simultaneously comparing first, second and third voltage levels to each data bit in clocked time increments wherein the magnitude of the increments is such that each binary data bit is in two of the three voltage levels and all data bits change each clock cycle, so that reconstructed signals of the binary information only may then be assembled based on a signal amplitude that is greater than a low threshold value that is less than the transition between the first and the second of the voltage levels and is less than a high threshold that is greater than the transition between the second and the third voltage levels. The reconstructed data signals are further shaped to be precise in timing, free of skewing and within the system clock.

Abstract: A decision sequence generating method and an associated receiver with a decision feedback equalizer (DFE) are provided. The receiver can mitigate multi-path distortion generated when data is transmitted through a multi-path channel, wherein the data is encoded into codewords, each of which comprises N chips. The receiver comprises a decision generator for generating N?1 chip decisions corresponding to first N?1 chips of a received codeword and for producing a codeword decision corresponding to the whole received codeword; and a feedback filter for reconstructing post-cursor section of the multi-path channel impulse response.

Abstract: This disclosure describes a flexible digital transmission system that improves upon the ATSC A/53 HDTV signal transmission standard. The system includes a digital television signal transmitter for generating a first Advanced Television Systems Committee (ATSC) standard 8-VSB bit stream and, for generating an encoded new bit stream capable of transmitting high priority information bits, wherein symbols of the new bit stream are capable of being transmitted according to a transmission mode selected from group comprising: a 2-VSB mode, a 4-VSB mode, and a hierarchical-VSB (H-VSB) transmission mode. Each respective 2-VSB, 4-VSB, and H-VSB mode is characterized as having symbols mapped according to possible symbol values from an alphabet comprising respectively, {?7, ?5, 5, 7}, {7, 3, ?3, ?7}, and {7, 5, 3, ?3, ?5, ?7}. The standard 8-VSB bit stream and new bit stream may be simultaneously transmitted over a terrestrial channel according to a broadcaster defined bit-rate ratio.

Abstract: Techniques are provided for tracking residual frequency error and phase noise in an OFDM system. At a receiver, each received OFDM symbol is transformed with an FFT to obtain received modulation symbols, which are serialized. A phase locked loop (PLL) operates on the serialized received modulation symbols and provides an independent phase correction value for each received modulation symbol. Each received modulation symbol is corrected with its own phase correction value to obtain a phase-corrected symbol. The phase error in each phase-corrected symbol is detected to obtain a phase error estimate for that phase-corrected symbol. The phase error estimate for each phase-corrected symbol is filtered (e.g., with a second-order loop filter) to obtain a frequency error estimate, which is accumulated to obtain a phase correction value for another received modulation symbol. The phase-corrected symbols are not correlated because independent phase correction values are used for the received modulation symbols.

Abstract: A digital signal of which input data has been segmented as block each having a predetermined data amount and highly efficiently encoded along with an adjacent block is decoded, edited, and then highly efficiently encoded. A delay that takes place in such signal processes is compensated. Thus, part of a digital signal that has been highly efficiently encoded digital signal can be edited.

Abstract: A GPS receiver and method using alternating “A” and “B” integration time segments. The polarities of certain GPS data bits are known beforehand and their expected reception times are known. The GPS signal in 10 millisecond “A” time segments and “B” time segments is depolarized according to the known polarities. The depolarized GPS signal during an “A” time period made up of all the “A” time segments is integrated for providing an “A” time period magnitude for each code phase. Likewise, the depolarized GPS signal during a “B” time period made up of all the “B” time segments is integrated for providing a “B” time period magnitude for each potential GPS code phase. The strongest of the time period magnitudes is compared to a correlation threshold for selecting a code phase for signal acquisition.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol group” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from the buffers having start symbols is temporarily suspended.

Abstract: An apparatus and a method for symbol decoding of baseband data in a wireless communications network is disclosed, and specifically CCK subsymbol prediction and symbol demodulation that occurs at 5.5 Mbps or 11 Mbps. The apparatus is configured to demodulate or predict the data differently, depending on the modulation rate. If the data was modulated at 11 Mbps, the ?3 rotator is rotated through each of its possible phase values and symbol correlation takes four clock cycles to complete. If the data was modulated at 5.5 Mbps, ?3 is not rotated with a set value of 0 within the correlator architecture, thereby saving power and reducing symbol correlation and subsymbol prediction to a single cycle while in such transmission mode.

Abstract: A novel method and apparatus for applying overlaid perturbation vectors for gradient feedback transmit antenna array adaptation is disclosed. The method and apparatus of the present invention allows a communication system to reduce transmit power that is associated with dedicated pilot signals by overlaying perturbation vectors and measuring channel estimates and demodulation channel estimates during a measurement time interval that comprises a plurality of feedback time intervals. The present inventive method utilizes channel estimates that include the effects of previous perturbation vectors, subsequent feedback vectors and intermediate feedback decisions. The inventive method extracts a coarse gradient estimate by utilizing a continuous summation of overlaid weight vector perturbation vectors and updates the weighting vector accordingly.

Abstract: A digital communications system includes a transmitter and a receiver. The transmitter is capable of quadrature amplitude modulation (QAM) encoding each bit of at least one n-bit digital signal into at least one QAM signal and thereafter transmitting the QAM signals. And the receiver is capable of receiving the QAM signals and thereafter integrating the QAM signals. The receiver includes at least one tapped-delay line filter, which can then receive the integrated QAM signals and thereafter output a representation of each bit of the at least one n-bit digital signal.

Abstract: A decoder of a data signal subjected to phase shifting keying (PSK) modulation uses a plurality of phase locked loops (801-1 to 801-n) having an inner decoder for short block codes, at least one of which is adapted to apply excess processing power to process a selected burst of the data signal, such as processing the burst with multiple initial phase/frequency error estimates. A selection circuit identifies the burst and supplies to said one of said plurality of phase-locked loops (801-1 to 801-n) for re-processing the bust with excess processing power. An outer Reed-Solomon block decoder (319) may be used to correct errors in the codewords from the phase locked loops and may be used in the selection of the burst by the selection circuit.

Abstract: The present invention relates generally to communication systems, both wired and wireless, employing a continuous phase modulation (“CPM”) waveform with a minimum shift keying (“MSK”) preamble. The present inventive system and method uses information from contiguous Fourier Transforms taken on contiguous data blocks to determine baud rate, phase, frequency offset, and bit timing of the CPM waveform or can be used to determine the frequency of continuous wave waveform. More particularly, the inventive system and method is applicable to the military satellite communications UHF frequency band for deciding whether a signal of interest is.

Abstract: Techniques to iteratively detect and decode data transmitted in a wireless (e.g., MIMO-OFDM) communication system. The iterative detection and decoding is performed by iteratively passing soft (multi-bit) “a priori” information between a detector and a decoder. The detector receives modulation symbols, performs a detection function that is complementary to the symbol mapping performed at the transmitter, and provides soft-decision symbols for transmitted coded bits. “Extrinsic information” in the soft-decision symbols is then decoded by the decoder to provide its extrinsic information, which comprises the a priori information used by the detector in the detection process. The detection and decoding may be iterated a number of times. The soft-decision symbols and the a priori information may be represented using log-likelihood ratios (LLRs).

Abstract: An apparatus and a method for decoding data that has been Complementary Code Keying (CCK)-encoded at one of the set of first and second differing data rates. The method includes receiving a symbol, determining which of the first and second data rates was used to encode the symbol and applying the symbol to a first correlator to generate a set of correlator output signals. The first correlator generates the set of correlator output signals based on a first mode when the first data rate was used to encode the symbol and based on a second mode when the second data rate was used to encode the symbol. The method also includes identifying a maximum-valued signal in one of the set of correlator output signals and demodulating the maximum-valued signal in one of the set of correlator output signals.

Abstract: A cooperative code-enhanced multiuser communications system having a receiver for resolving user ambiguity in a received composite signal by using convolutional encoder state machine properties to analyze strings of bit sums and separate out individual user data. The receiver comprises a signal sampler which converts a received composite signal to a digital data. A single point cluster mapper determines a closest pseudo-constellation point, and the pseudo-constellation point is formed with the aid of power and timing control in the transmitters. A bit sum look-up table maps symbol points to bit sums. A deterministic loop tests for bit sum cases where symbols can be determined immediately. A guess loop tests the bit sum after the deterministic loop test and performs guesses until all bits are decided. The bit sum is provided to a multiuser convolutional decoder to decide all user data streams.

Abstract: Canceling images in a quadrature modulator includes frequency shifting the baseband signal and images; filtering the frequency shifted baseband signal and images; phase and frequency shifting the baseband signal and images; filtering the phase and frequency shifted baseband signal and images; combining the filtered frequency shifted baseband signal and images with the filtered phase and frequency shifted baseband signal and images to suppress the negative frequency images and isolate the modulated baseband signal.

Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.