Abstract: A Signal Conditioning Filter (SCF) and a Signal Integrity Unit (SIU) address the coupled problem of equalization and noise filtering in order to improve signal fidelity for decoding. Specifically, a received signal can be filtered in a manner to optimize the signal fidelity even in the presence of both significant (large magnitudes of) ISI and noise. The present invention can provide an adaptive method that continuously monitors a signal fidelity measure. Monitoring the fidelity of a multilevel signal can be performed by external means such as by the SIU. A received signal y(t) can be “conditioned” by application of a filter with an electronically adjustable impulse response g(t). A resulting output z(t) can then be interrogated to characterize the quality of the conditioned signal. This fidelity measure q(t) can be used to adjust the filter response to maximize the fidelity measure of the conditioned signal.

Abstract: A method and a system for reliably supplying information about an electronic device employed as a primary information signal receiver device to an electronic device employed as a primary information signal sender device via an existing analog transmission line or digital serial transmission line. A set top box (STB) employed as the primary information signal sender device and a VTR (video tape recorder) employed as the primary information signal receiver are connected to each other via an analog transmission line.

Abstract: A transmission and reception method permits simultaneous use of multiple remote controllers at the same frequency to a single receiver without mutual interference. A transmission period consists of a transmission enabled period for transmitting a transmission signal from a remote controller, and a transmission disabled period for disabling the signal transmission. Individual remote controllers can repeat the transmission. For the individual remote controllers, one period of the transmission period is 2i (“I” is a natural number equal to or more than 3, and is set to a proper number different from one channel to another) times a unit transmission period.

Abstract: A method and apparatus controls a plurality of receiver channel elements (102a–102n), such as RAKE receiver fingers in a CDMA receiver, by assigning a real time priority metric to each channel type. For example, a receiver channel element management module (109) generates a channel weight value (216) and a receiver channel element factor value (218). The channel weight value (216) is dynamically determined on a per channel type basis representing an extent of energy demanded by a channel. For example, a channel at a higher rate may be programmed to start off with higher energy needs as compared to a different channel type, such as a voice channel which may communicate information at a lower rate. The receiver channel element factor value (218) is used to determine an impact of deassigning receiver fingers so that the dropped receiver finger is the one that is least harmful to all channels.

Abstract: A transient pre-emptor includes a processor configured to detect transients in a communications system. After the processor detects a transient in the communications system, it causes a data communications equipment to suspend or reduce data transmission during the occurrence of a subsequent transient.

Abstract: A method of transmitting QPSK digital signals in which each 2-digit binary number, referred to as a symbol, is assigned a phase of a carrier, and symbols are added to enable error correction at the receiver. The error correction code is a product code. To obtain transparency to phase rotations, the I bits (I1, I3, etc.) and the Q bits (Q2, Q4, etc.) of a symbol to be transmitted are placed in different rows but in the same column, so that each row contains only one type of bit, I or Q. The error correction coding is effected: row by row (NC-KC), and by pairs of adjacent columns, and the code I (or Q) bits of two associated adjacent columns are deduced from the I (or Q) bits of the two columns.

Abstract: A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

Abstract: The present invention relates to an improved method of de-jittering MPEG-2 and MPEG-4 data that is transmitted over a network. First, a network system jitter associated with periodic reference data packets is estimated. Then, the estimated system jitter is used to adjust clock-stamped reference values in the data packets before they are provided to the PLL for clock synchronization. The invented de-jittering method improves the PLL's ability to synchronize the MPEG data and provides for a better quality playback.

Abstract: A voice and data communication system whereby a line card digitizes and packetizes voice communications signals upon the failure of Customer Premises Equipment (CPE). The system comprises a line card for coupling the CPE with a network. Furthermore, the invention provides a system that can direct the voice signals to either or both of a voice network and a data network.

Abstract: A PWM signal is made to rise synchronously with a pixel clock by inputting of a pulse to a set terminal (S terminal) of an R-S flip-flop. One of a reference clock, which is generated by a reference clock generator, and a delay clock, which is obtained by a delay circuit delaying the reference clock, is selected in accordance with delay selection data. The PWM signal is made to fall synchronously with a selected clock.

Abstract: In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.

Abstract: In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted.

Abstract: A demodulation apparatus for a base station of a CDMA mobile communication system is provided, having an analog-to-digital converter device to convert an intermediate frequency signal into a digital signal and provide a quadrature component and an in-phase component of the digital signal, a plurality of filters to filter the components of the digital signal in the low pass band respectively, and a CDMA modem to demodulate the outputs of the plurality of filters. Since direct control by the digital signal of the base-band I channel and Q channel at the intermediate frequency can be performed and the analog-to-digital converter simultaneously performs the QPSK demodulation and the analog-to-digital conversion, the circuit design can be simplified and the characteristics reducing the noise can be obtained.

Abstract: A method and apparatus for data communication using signature sequences and spread spectrum techniques to reduce the effects of certain transmission impairments in a Wireless local area network (WLAN). The invention uses a number of correlators and M-ary Code Keying with a Supergold signature sequence for simultaneously generating a periodic signal for acquiring symbol synchronization, a difference squarewave signal for acquiring and maintaining chip synchronization and a sum signal for determining received signal strength and setting threshold levels.

Abstract: A modulator, and demodulator, apparatus and method for use in a multiple sub-channel communication system is taught. A commutator is employed for fractionally sampling, or distributing, signals from, or to, a multiple channel polyphase filter. The filter is coupled with a discrete Fourier transform, or its inverse, such that the relationship between the base-band sampling rate of a plurality of sub-channel signals, the frequency spacing of the sub-channel signals, and the sampling rate of a composite signal can be related by any rational number, thereby freeing designers to optimize system design respecting channel spacing, bandwidth, and signaling rates. The advantages of the present invention are realized by adjusting the interpolation and decimation rates of the filter, and by adjusting the resolution and decimation rates of the transform.

Abstract: In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal.

Abstract: A GPS receiver and method using alternating “A” and “B” integration time segments. The polarities of certain GPS data bits are known beforehand and their expected reception times are known. The GPS signal in 10 millisecond “A” time segments and “B” time segments is depolarized according to the known polarities. The depolarized GPS signal during an “A” time period made up of all the “A” time segments is integrated for providing an “A” time period magnitude for each code phase. Likewise, the depolarized GPS signal during a “B” time period made up of all the “B” time segments is integrated for providing a “B” time period magnitude for each potential GPS code phase. The strongest of the time period magnitudes is compared to a correlation threshold for selecting a code phase for signal acquisition.

Abstract: A transmission method uses multiple kinds of control codes to be exchanged on a serial transmission path between a sender side and a receiver side, and each of the multiple kinds of control codes has bits smaller in number than a predetermined fixed length.

Abstract: A digital passband matched filter is automatically adapted to a carrier wave ? in accordance with a frequency offset of the carrier wave, to obtain a passband digital signal having no frequency distortion due to the frequency offset. Thus, a receiver in which drawbacks such as decrease of SNR and increase of circuit complexity caused by the fixed baseband/passband matched filter is obtained. Since a cosine wave generating section operates in a carrier wave frequency restoring mode and a carrier wave frequency adaptive mode, respectively, a single cosine wave ROM table can be used regardless of the respective operating modes, thereby reducing circuit complexity. Since the digital passband matched filter acts to renew the filter coefficients adapted to the carrier wave adaptive mode only, power consumption required to operate the filter can be minimized.

Abstract: A dual-radio communication apparatus has a first radio device, such as a Bluetooth radio, for use in a first frequency band, and a second radio device, such as a Globalstar satellite radio, for use in a second frequency band, which is proximate to the first frequency band. The communication apparatus also has a controller coupled to the first and second radio devices. The first radio device may comprise a frequency-hopping spread-spectrum transmitter. Moreover, the first radio device has a first operating mode employing a first frequency range. The first radio device also has a second operating mode employing a second frequency range, which is smaller than the first frequency range. The controller is adapted to set the first radio device in its second operating mode, when the second radio device is in operation, and otherwise set the first radio device in its first operating mode.