Abstract: A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.

Abstract: A switch controlling section 204 controls a switching device 205 and a switching device 211 such that mode information, which shows that a current state of an apparatus is an initial synchronous mode, which is a power-on time, or a standby mode, which is a cell moving time, is input, correlation processing is performed by a matched filter 209 in the initial synchronous mode, and correlation processing is performed by a sliding correlator 210 in the standby mode. This makes it possible for a CDMA radio communication system to establish initial synchronization at high speed and to improve a reduction in current consumption.

Abstract: The invention relates to a method for equalizing a signal with a frame structure, received via a time-variable transmission channel. According to said method, a frame-type equalization is used. The channel unit pulse response is analyzed and one equalization alternative is selected from several provided alternatives. According to the principle of equalization with decision feedback, it is preferable if only two alternatives are provided; a conventional forward equalization and an inverse-time reversed equalization. A decision in favor of one or the other of these alternatives can be made simply based on the sign characterizing the so-called skewness.

Abstract: By application of a method and a circuit for retiming one or several digital data signal(s) (Din) each consisting of a number of successive bits, wherein the data signal is sampled by an internal clock signal (Ckint) generated from an external clock signal (Ckref), the internal clock signal (Ckint) is phase locked to the data signal (Din) so that the latter is sampled approximately in the centre of every bit. By generating the internal clock signal from the external clock signal, and at the same time phase locking it to the data signal, the internal clock signal will automatically adjust itself so that the data signal is sampled at the appropriate point in time, i.e. in the centre of the bit period. As a result, there are no strict requirements as to the synchronisation between the data signal and the clock signal, and an individual adjustment of the synchronisation in preceding circuits is thus avoided.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels. In one embodiment, the frequency down-conversion is performed in a single down-conversion process, and the ADC (20) employs delta-sigma processing to provide digital conversion over the complete frequency band.

Abstract: A wideband predistortion system compensates for a nonlinear amplifier's frequency and time dependent distortion characteristics. The system comprises a data structure in which each element stores a set of compensation parameters (preferably including FIR filter coefficients) for predistorting the wideband input transmission signal. The parameter sets are preferably indexed within the data structure according to multiple signal characteristics, such as instantaneous amplitude and integrated signal envelope, each of which corresponds to a respective dimension of the data structure. To predistort the input transmission signal, an addressing circuit digitally generates a set of data structure indices from the input transmission signal, and the indexed set of compensation parameters is loaded into a compensation circuit which digitally predistorts the input transmission signal.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.

Abstract: Disclosed herein is a method of receiving a spread-spectrum signal in a radio communication terminal device having a plurality of demodulators for demodulating a received spread-spectrum signal, comprising the steps of detecting when at least one of a plurality of demodulators is temporarily unable to properly demodulate the received spread-spectrum signal, determining whether or not there is a demodulator which is not being used other than the at least one of the demodulators, and continuing a demodulating process of the at least one of the demodulators, if there is a demodulator which is not being used. Thus, according to the present invention, the time in which the demodulator is unlocked is minimized, and a stable, high-quality signal can be received.

Abstract: A method reduces interference adaptively in a CDMA receiver. A baseband signal is demodulated to determine target symbols. The baseband signal is also demodulated to estimate interfering symbols. The interfering symbols are modulated to generate a cancellation signal, and the cancellation signal is subtracted from the base band signal to reduce interference in the target symbols.

Abstract: When the average received signal level falls below a given threshold level, a received level detecting/monitoring section informs a microprocessor of it. The microprocessor then collects information of the arrival direction and received power of desired radiation from each terminal station and the arrival direction and received power of undesired radiation from each source of undesired radiation and recalculates amplitude and phase weight values. The microprocessor rewrites weight values already entered into a weight value table by the recalculated weight values to thereby alter amplitude and phase weight values for antenna elements of an array antenna. Thereby, the directivity of the array antenna is subjected to optimum control according to variations in electromagnetic radiation propagation environment, allowing good radio communications at all times.

Abstract: A searcher for a CDMA receiver apparatus includes a correlator obtaining a correlation value between a spreading code sequence and a spreading code sequence within a received signal, and a non-linear processor carrying out a non-linear conversion to convert one of the correlation value and a predetermined value indicative of the correlation value into correlation value information which has a data width smaller than that of the one of the correlation value and the predetermined value. The correlation value information is used to carry out a search process to search for a synchronizing timing with respect to the spreading code sequence within the received signal.

Abstract: A system and method for synchronizing the skip pattern to two clock domains and initializing the clock skipping buffer which enables data transfers between the two clock domains. In one embodiment, a circuit comprises a pair of alignment detection units, a synchronous reset unit, a skip pattern generator, a counter reset unit and a data transfer buffer. Each of the alignment units is configured to detect the alignment of the clock signal in one of the clock domains with a reference clock signal and generate a signal indicative of the alignment. This signal is conveyed to the synchronous reset unit and the counter reset unit. The alignment signal generated by one alignment unit is also conveyed to the skip pattern generator. The synchronous reset unit accepts the alignment signals from the alignment units and generates concurrent reset signals (i.e., one for each of the two clock domains) to initialize the counter reset unit.

Abstract: An apparatus for resynchronizing data between two modules sharing a common clock where the common clock is delayed at the second module has means for storing multiple copies of the data in the first module in a recirculating manner using a Johnson counter to cycle through storage locations. A multiplexer in the second module has the copies from the first module as inputs and selects in response to a select signal generated from the delayed version of the common clock and an enable signal from the Johnson counter synchronizing each of the copies in turn such that the copy selected has just not been written or is just not about to be written to assure that the data is in a stable state.

Abstract: A code generator capable of performing the shift operation at high speed on a small circuit scale by providing combination circuits (matrix operation weights) in response to the shift count. The code generator has a register 10, a selection circuit 11, combination circuits 12 to 16 for performing matrix operation, and a control circuit 17 for controlling the timing of storing data in the selection circuit 11 and the register 10. One of the combination circuits 12 to 16 is selected in response to a select signal S from the control circuit 17 and data is output from the register 10 in response to a register storage clock Rck.

Abstract: A technique for calibrating a N-port receiver, such as for example a 5- or 6-port receiver is proposed. The N-port receiver (1) comprises a first input (2) for a RF signal to be detected, a second input (3) for a RF signal originating from a local oscillator (4) and N−2 output terminals. Calibrating signals are generated on the basis of the RF signal supplied by the local oscillator (4). The calibration signals are fed to the first input (2) and/or the second input (3) of the N-port receiver (1). Calibration coefficients are calculated on the basis of the output signals generated by the N-port receiver (1) in response to the feeding of the calibration signals. The calibration signals are unmodulated signals and are only processed by means of a passive RF circuitry in the calibration device (100). The solutions according to the present invention allow a simple calibration of N-port receivers, which can be used as IQ demodulators or converters.

Abstract: A method of encoding a plural-bit data word as a plurality of multi-level symbols, where each of the plurality of multi-level symbols has a value selected from a predetermined plurality of levels. The method includes first translating each one of the selected bit positions of the plural-bit data word to one of the levels. When the contents of a predetermined one of the bits of the data word is a predetermined value, the method provides a second translation of each of the selected bit positions of the plural-bit data word to one of the levels. The method further includes generating a plural-bit offset word from predetermined bit positions of the data word and generating the multi-level symbols by addition of the offset word to the translated levels. One embodiment of the invention provides that the multi-level symbols are assigned a five-level code and the codes are treated as twos-complement numbers.

Abstract: A circuit is designed with a measurement circuit (746) coupled to receive an input signal from at least one of a first antenna and a second antenna of a transmitter. The measurement circuit produces an output signal corresponding to a magnitude of the input signal. A control circuit (726) is coupled to receive the output signal, a first reference signal (&eegr;1) and a second reference signal (&eegr;2). The control circuit is arranged to produce a control signal in response to a comparison of the output signal, the first reference signal and the second reference signal.

Abstract: A transmission power control method of measuring an Eb/N0 after weighted signals are combined is disclosed. A plurality of rake receivers detect respective received signals for respective paths, delay demodulated data which are the detection result based on a set delay time, and then combine and output the demodulated data. A multipath searcher acquires reception delay information which is information on a delay time among the respective paths contained in the received signals. A rake receiver control unit sets the delay times for the rake receivers based on the reception delay information acquired by the multipath searcher. A plurality of first weighting units weight the demodulated data output from the respective rake receivers. A first combining unit combines the signals weighted by the first weighting units into one signal. An Eb/N0 measuring unit measures an Eb/N0 of the demodulated data combined by the first combining unit.

Abstract: When switching to a path whose directivity changes greatly or a path with a widely different propagation delay, transmission is performed for both directivities for a certain period of time. Then, transmission is performed for one directivity. When the switching of transmission directivities is controlled, this allows correct reception of signals and prevents instantaneous interruption due to loss of synchronism even if transmission is performed by switching to a path with a widely different propagation delay.

Abstract: An apparatus for acquiring a pseudo noise (PN) code and a direct-sequence code division multiple access (DS-CDMA) receiver are provided.