Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.

Abstract: Apparatus and methods are provided for exploiting the existence of a shortest path between a source device and a destination device by identifying the shortest path and using the signal which has taken the shortest path in preference to delayed transmissions or delayed images of the same signal, thereby improving signal distribution. The present invention provides a processor between a phase-sensitive detector and a low pass filter of a phase locked loop for selecting and driving the PLL primarily from the signal which has taken the shortest path.

Abstract: In a wireless telecommunications system, data processing delays associated with digital channelization and de-channelization may be reduced through the use of a technique that involves processing data blocks in conjunction with the transformation of the data blocks by a large, Fast Fourier Transform (FFT) algorithm, and makes use of multiple transmission and reception branches. In accordance with this technique, the processing delays associated with the FFT algorithm are minimized, but not to the detriment of other important channelizer/de-channelizer design characteristics, such as power consumption, die area and computational complexity.

Abstract: A unified, unidirectional serial link is described for providing data across wired media, such as a chip-to chip or a card-to-card interconnect. It consists of a transmit section and a receive section that are operated as pairs to allow the serial data communication. The serial link is implemented as part of a VLSI ASIC module and derives its power, data and clocking requirements from the host modules. The logic transmitter portion contains a phase locked loop (PLL), a dibit data register, a finite impulse response (FIR) filter and a transmit data register. The phase locked loop comprises both a digital coarse loop and an analog fine loop. The digital receiver portion contains a PLL, an FIR phase rotator, a phase rotator control state machine, and a clock buffer. The transmitter and the receiver each preferably utilize a pseudo-random bit stream (PRBS) generator and checker.

Abstract: In addition to a first transmitter circuit, a plurality of transmission lines and a first data processing circuit in the receive side, so as to cause a DLL circuit to be regulated that regulates timing of a sampling clock of the data signal, a second first transmitter circuit, a transmission line and a second data processing circuit are provided, when a second specific signal string is sent, a regulation start signal string is caused to be distributed by the second data processing circuit, regulation is caused to be made for a DLL circuit of the first data processing circuit by a regulation signal string, the data starting with the bit next to a first specific signal string detected in the data signal is written into a m-address n-bit FIFO circuit, simultaneously a read address synchronized with a system clock is generated from a third specific signal string that came to the second data processing circuit, whereby the data is recovered.

Abstract: A channel evaluator acquires a change predicted value from a known symbol, and a compensator compensates for a first symbol using the change predicted value. A demodulator restores a portion corresponding to this symbol with another subcarrier. A replica generator acquires a transmission replica of the restored symbol. The channel evaluator performs complex division on the replica with the symbol to acquire an amplitude phase ratio. A detector compares the amplitude phase ratio with an amplitude phase ratio acquired immediately previously. In case where an elimination condition is satisfied, the detector disregards the amplitude phase ratio acquired currently and uses an immediately previous value instead, an averaging unit averages amplitude phase ratios to acquire a next change predicted value, and the compensator compensates for a next symbol using the change predicted value. Hereinafter, the sequence of processes is repeated.

Abstract: A method for estimating channel parameters of radio channels of a W-CDMA mobile radio system, for example in accordance with the UMTS standard includes transmitting sequences of known symbols between unknown data symbols by a base station. The channel estimation is carried out by a comparison of the received sequences with the known symbols, and the result of the comparison is integrated over a sequence of known symbols.

Abstract: The invention relates to a communications network (1) comprising a plurality of network nodes (2), which include each a synchronization circuit (5) for generating a global clock signal (GT) from a local clock signal (LT) formed by a clock generator (4) in dependence on a time of reception of a message. The synchronization circuit (5) includes a divider arrangement (8) for dividing the local clock signal (LT) in dependence on a correction term (KT) and at least one divider factor which is produced by a scaler arrangement (9). The comparator circuit (10) is provided for forming the correction term by comparing the instant of reception of a message and of the local clock signal LT. Furthermore, the synchronizing circuit (5) includes a divider control (7) which may perform a change of at least one divider factor when the correction term (KT) exceeds a predefined first threshold.

Abstract: A digital signal is transformed in at least two different frequency bands according to at least two different resolutions. The signal is divided into first blocks all having the same predetermined first number of samples. Each of the first blocks is transformed into a plurality of second blocks, any second block under consideration having a second respective number of samples which depends on the resolution of the second block under consideration, and containing samples selected according to their frequency. Second blocks issuing from the transformation of different first blocks are grouped in order to form third blocks all having the same predetermined third number of samples which is at least equal to the largest of the second numbers.

Abstract: A method for the linearization of a wide frequency band power amplifier. The frequency band of operation of the amplifier is divided into at least two groups or subbands. The instantaneous frequency of each sampled input signal is measured in order to determine the group or subband to which it belongs, and predistortions are applied to the input signal, these predistortions depending on the frequency group. The method is particularly useful for the linearization of a power amplifier of a transmitter.

Abstract: A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

Abstract: A system and method for measuring the Ricean K-factor of a wireless channel in real time are provided. An amplitude sample of a transmitted RE waveform of either fixed or varying amplitude is low-pass filtered to eliminate high frequency noise if present. The magnitude squared of the filtered sample amplitude is squared to obtain the power gain of the sample and the magnitude squared of the power gain is computed. The sums of a window of power gains and the sum of the squares of the power gains are then updated. These sums of the window of amplitude samples are then averaged to estimate the first and second moments of the window of samples. The averages are low-pass filtered to minimize fluctuations. The final average is input to a moment-based set of Greenstein-Michelson-Erceg (GME) equations to obtain estimates for the time average of the power gain and rms deviation of the power gain. The K-factor is calculated in accordance with these equations and low-pass filtered to smooth the result.

Abstract: A digital signal of which input data has been segmented as block each having a predetermined data amount and highly efficiently encoded along with an adjacent block is decoded, edited, and then highly efficiently encoded. A delay that takes place in such signal processes is compensated. Thus, part of a digital signal that has been highly efficiently encoded digital signal can be edited.

Abstract: Systems and methods for processing a received radio signal in a communication system are described. Initial time synchronization is acquired using a trace operator. Then, a number of channel taps for use in further processing is determined based on the initial time sync, also using a trace operator. A final synchronization position is then selected using the number of channel taps and, if multiple branches are employed to receive the signal, using a determinant-based technique. Finally, a channel estimate is determined using the final synchronization position.

Abstract: A method is provided for monitoring transmission signal interference in a bi-directional transmission/reception system in which a modulated signal received at a receiver location is subjected at the receiver location to analog to digital (A/D) conversion by an A/D converter 3, an output of which is routed to an input of a digital demodulator 6 for demodulation. The method includes the steps of accessing the output of the A/D converter 3 before the output is subjected to demodulation by the demodulator 6 and storing the accessed data in a storage buffer 7. The data stored in the storage buffer 7 is available for inspection to assist in determining the presence of signal interference.

Abstract: A data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels with signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.

Abstract: A communications processor is presented that is capable of receiving a potentially degraded data transmission signals operating at high transmission rates and generating an improved data transmission signal in a manner that allows the signals to be transmitted over longer distances than is otherwise possible using conventional methods. The communications processor includes a decoding mechanism configured to compensate for amplitude and phase distortions of the data transmission signal, to split the corrected data signal into component data signals, to generate a data clock reference signal based on the data transmission signal and the external clock reference signal, and to convert the component data signals into digital component data signals synchronized to the data clock reference signal.

Abstract: A method and apparatus reliably encode and decode information over a communication system. The method includes transforming two coefficients into two pairs of random variables, one random variable in each pair having substantially equal energy as one random variable in the other pair. The method further includes quantizing each of the pairs of random variables and entropy coding each quantized random variable separately creating an encoded bitstreams. The encoded bitstreams are received by a decoder which first determines which channels of the communication system are working. The encoded bitstream is entropy decoded, inversed quantized and inversed transformed. An inverse transform performs three different transformations depending upon which channels are working, i.e., whether the first, second or both channels are working.

Abstract: A direct sequence CDMA receiver is disclosed that includes an interpolative delay profile production unit. An A/D converter receives signals that have been received by an antenna and converted to a baseband signal and samples the signals at twice the chip rate. A matched filter finds correlation values with the received data using a spreading code of 1/−1, and the delay profile production means interpolates these correlation values by means of, for example, a filter. A timing detector selects delay profiles in descending order of size, and extracts the timings of each. A despreader interpolates the spreading code to synchronize with the timing signals, and using these interpolated values carries out despreading of the received data. A mixer carries out RAKE/diversity mixing of the despread signals.

Abstract: A receiver (10) for a wireless telecommunications system that provides relatively wideband signal processing of received signals without increased signal distortion so that multiple received signals can be simultaneously processed. The receiver (10) includes a specialized LNA (16), frequency down-converter (18) and ADC (20) to perform the wideband signal processing while maintaining receiver performance. The frequency down-converter (18) employs a suitable mixer (28), BPA (32), attenuator (34), and transformer (36) that are tuned to provide the desired frequency down-conversion and amplitude control over the desired wideband. The down-converter devices are selected depending on the particular performance criteria of the ADC (20). A specialized digital channelizer (22) is included in the receiver (10) that receives the digital signal from the ADC (20), and separates the signals into the multiple channels.