Abstract: A first counter measures the span of the start bit of a first character of an AT command transmitted from a DTE based on instructions from an MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock. A shift register receives data subsequent to the start bit of the first character based on the sampling clock from the second register, holds the received data, which data is then read by the MPU.

Abstract: A method for training a modem includes selecting a transmission rate from one of a plurality of bauds, each baud identifying at least one transmission rate. The method also includes attempting to train the modem at the transmission rate and measuring the signal quality after the modem trains. The method further includes accessing a table of acceptable signal qualities, the table corresponding to the baud of the first transmission rate. In addition, the method includes comparing the measured signal quality to at least one acceptable signal quality identified by a provisioned margin in the table to determine if the measured signal quality is acceptable.

Abstract: A method and apparatus for reducing processing requests of a pool of soft modems is disclosed. In one embodiment, a remote access concentrator comprises a memory, a processor, an interface bus, and a host interface. In one embodiment, the processor is coupled to the memory to operate a pool of soft modems in parallel with a common retrain handler, the common retrain handler includes a queue to store retrain requests, a request management block to retrieve the retrain requests and to identify modems that correspond to the retrain requests within a period of time, and a retrain engine to perform retrain procedures in accordance with modem standards.

Abstract: A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit (4), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180°, which are included in a carrier reproduction phase difference detecting circuit (8), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit (10) so that the phase obtained from the signal point position coincides with the phase convergence point.

Abstract: A predistortion system adaptively compensates for distortion introduced along one or more amplification chains of a power amplifier system. In one embodiment, the predistortion system includes a plurality of compensation circuits, each of which is coupled to, and configured to digitally predistort an input transmission signal to, a respective amplification chain of an antenna array system. Each such amplification chain has an output coupled to a respective antenna of the antenna array system. A processing unit monitors the input transmission signals to, and corresponding output signals from, each of the amplification chains on a time-shared basis, and generates updates to the compensation parameters used the corresponding compensation circuits.

Abstract: An adapter that buffers received symbols and automatically determines and corrects for skew between lanes is disclosed. In one embodiment, the adapter is a part of a network that includes a first and second devices coupled together by a communications link having multiple independent serial lanes. The first device Initiates communication by repeatedly transmitting a training sequence that includes a start symbol for each lane. An adapter in the second device includes a set of buffers each configured to receive the symbols conveyed by a corresponding serial lane. The buffers are coupled to a reconstruction circuit that removes one “symbol groups” at a time from the buffers. A symbol group is made up of one symbol from each buffer. The reconstruction circuit removes symbol groups until a start symbol is detected. If the start symbol is not detected in all buffers, output from buffers having start symbols is temporarily suspended.

Abstract: A digital data reproducing apparatus and method are provided, which are capable of reproducing both digital audio data from the main body of the apparatus and digital data from an external interface, using a simple construction. A main body of the apparatus processes first digital data, an interface receives, from an external device independent of the main body, second digital data having a sampling rate asynchronous with and different from a sampling rate of the first digital data, the first and second digital data being reproduced by the main body. The first digital data are oversampled at a frequency n times the sampling rate of the first digital data. The first digital data oversampled by the filter device and the second digital data input via the interface are added together, and the resulting data are converted into an analog signal.

Abstract: Methods and systems for data rate detection for multi-speed embedded clock serial receivers are described. In one embodiment, a method of determining a data rate of a high speed serially transmitted data stream comprises statistically examining edge characteristics of the incoming data stream. Based on the edge characteristics, a signature is identified that is associated with the edge characteristics. Based on the identified signature, a data rate at which the data stream is being transmitted is determined. In one embodiment, a clock extraction/data recovery circuit is provided for recovering an embedded clock and data from a high speed serially transmitted data stream. The circuit comprises a phase comparator that is configured to receive a high speed serially transmitted data stream and output indicia whenever the data stream experiences a data transition. A voltage controlled oscillator (VCO) is connected with the phase comparator and provides a clock signal having clock edges.

Abstract: A method for synchronizing multi-carrier signals in an orthogonal frequency division modulation (OFDM) data transmission system is disclosed which provides maximum likelihood estimation of timing offset and frequency offset. The estimates are able to compensate the estimation error over an entire span of observed data samples. The method requires no training sequence thus enabling blind frequency compensation. The method provides a joint probability density function for the estimates which consists of two terms; one generated from observed data received during a first interval and one generated from observed data received during a second, following, interval. The estimates provided by the method are therefore maximal likelihood over the entire span of observed signals and are a significant improvement over estimates provided by methods based only observations during the first interval. The method is mathematically robust and computationally and statistically efficient.

Abstract: A system, device, and method for time-domain equalizer (TEQ) training determines the TEQ order and TEQ coefficients by applying the multichannel Levinson algorithm for auto-regressive moving average (ARMA) modeling of the channel impulse response. Specifically, the TEQ is trained based upon a received training signal. The received training signal and knowledge of the transmitted training signal are used to derive an autocorrelation matrix that is used in formulating the multichannel ARMA model. The parameters of the multichannel ARMA model are estimated via a recursive procedure using the multichannel Levinson algorithm. Starting from a sufficiently high-order model with a fixed pole-zero difference, the TEQ coefficients corresponding to a low-order model are derived from those of a high-order model.

Abstract: In a method of transmitting data over a communications channel, at least some of the bits of an incoming bit stream are passed through a turbo encoder to generate turbo encoded output bits, and words corresponding to symbol points on a constellation in a trellis code modulation scheme are generated using at least the bits passed through the turbo encoder, possibly in conjunction with other bits that are not passed the through the turbo encoder. Typically, the turbo encoded bits are the least significant bits.

Abstract: A network receiver is configured for receiving a modulated carrier signal representing a data frame from another network transceiver via a network medium, the modulated carrier signal may be either a pulse position modulated (PPM) carrier, a quadrature amplitude modulated (QAM) carrier, or a compatibility mode frame including both PPM and QAM portions. The network receiver is configured to select an A/D sampling clock frequency corresponding to the detected frame type.

Abstract: A system for outputting pseudorandom noise sequences comprises a plurality of output apparatuses.

Abstract: A receiving unit is more precisely synchronized to a transmitting unit by transmitting synchronization signals from the transmitting unit, adjusting a clock-pulse generator of a phase-locked loop, a phase shifter integrating instantaneous phase errors to an integration value, and adjusting the integration value to an integration fraction that is less than one.

Abstract: A standard clock 34 is input to a phase comparator 52 and a phase controller 56. The ring oscillator 50 oscillates a shift clock 70 having a same cycle as the standard clock 34. The phase comparator 52 matches the downward shift of the shift clock 70 with the downward shift of the standard clock 34 to output a shift clock 72. The shift clock 72 is supplied to the pulse inserter 54. The phase controller 56 receives the standard clock 34 and generates a phase control signal 74 indicating cycles of the shift clock 72 to which the insert-pulses are inserted among a plurality of cycles of the shift clock 72. The pulse inserter 54 inserts the insert-pulses to the cycles of the shift clock indicated by the phase control signal 74. The phase-lock unit 58 generates a delay clock 82 by delaying the phase of the shift clock 70 oscillated by the ring oscillator 50 with respect to the phase of the standard clock, based on the standard clock and the shift clock 76 including the insert-pulses.

Abstract: Display of signals containing inter-symbol interference (ISI). An input signal is modeled as comprising an ideal signal plus ISI plus error. In a first embodiment of the invention, an error signal and an ideal signal are derived from the input signal. The ideal signal is combined with the error signal producing an ideal signal with errors. In a second embodiment of the invention, a first signal comprising the ideal signal plus ISI plus error is derived. A second signal comprising only ISI is derived, and subtracted from the first signal, producing a signal containing the ideal signal plus error.

Abstract: A bit encoding system for use with a bus (7) of a distributed microcontroller network (200,300), includes a waveform generator (100) for generating a substantially sinusoidal waveform. A modulation arrangement (340, 341) is arranged to amplitude modulate the waveform between first and second amplitudes to define first and second data values. A zero crossing point of the waveform is used to define timing information for the bus (7).

Abstract: A prescaler (200) includes a first frequency divider (204, 206) configured to receive an input signal at an input frequency. The prescaler further includes a phase rotator (208) coupled to the first frequency divider to produce a plurality of signal phases in response to the input signal. A frequency control circuit (214) is configured as a one-hot decoder to select one signal phase of the plurality of signal phases. The one-hot decoder provides maximum speed of operation of the prescaler by eliminating decoding of the feedback signal.

Abstract: When multiplexing channels which conduct communication at various transmission rates, each communication is made capable of conducting communication processing, such as information reception, with a minimum required processing amount needed by itself. A plurality of communication channels are set in a predetermined band, and communication in each of the set channels is performed by using a multi-carrier signal having transmission symbols distributed among a plurality of subcarriers. Transmission symbols of each channel on a frequency axis are arranged at intervals of an Nth power of 2 (where N is an arbitrary positive number) with respect to a reference frequency interval for transmission. From the transmission signal, a signal component of a required channel is received.