Patents Examined by Raj R Gupta
  • Patent number: 11955425
    Abstract: Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCOTR MANUFACTURING CO., LTD.
    Inventors: Fang Chen, Jhon Jhy Liaw, Min-Chang Liang
  • Patent number: 11949010
    Abstract: A metal-oxide-semiconductor device can include: a base layer; a source region extending from an upper surface of the base layer to internal portion of the base layer and having a first doping type; a gate structure located on the upper surface of the base layer and at least exposing the source region, and a semiconductor layer located on the upper surface of the base layer and having the first doping type, where the semiconductor layer is used as a partial withstand voltage region of the device, and the source region is located at a first side of the gate structure, the semiconductor layer is located at a second side of the gate structure, and the first side and the second side of the gate structure are opposite to each other.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: April 2, 2024
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Budong You, Chunxin Xia
  • Patent number: 11949044
    Abstract: A display device and a method of manufacturing the same are provided. The display device includes a first alignment electrode and a second alignment electrode spaced apart from each other, a light emitting element between the first alignment electrode and the second alignment electrode, a first auxiliary electrode at a first side of the light emitting element in a plan view, and separated from the first alignment electrode, and a second auxiliary electrode at a second side of the light emitting element in a plan view, and separated from the second alignment electrode, wherein an alignment signal is configured to be applied to the first alignment electrode, and wherein a first auxiliary signal of a phase that is different from a phase of the alignment signal is configured to be applied to the first auxiliary electrode.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: April 2, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Buem Joon Kim, Hyun Deok Im
  • Patent number: 11935918
    Abstract: An integrated circuit (IC) device comprises a high voltage semiconductor device (HVSD) on a frontside of a semiconductor body and further comprises an electrode on a backside of the semiconductor body opposite the frontside. The HVSD may, for example, be a transistor or some other suitable type of semiconductor device. The electrode has one or more gaps directly beneath the HVSD. The one or more gaps enhance the effectiveness of the electrode for improving the breakdown voltage of the HVSD.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Hsin Fu Lin, Tsung-Hao Yeh
  • Patent number: 11935923
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor with gated collector and methods of manufacture. The structure includes: an extrinsic base region vertically over a semiconductor substrate and comprising asymmetrical sidewall spacers on opposing sidewalls of the extrinsic base region; a collector region on the semiconductor substrate and separated from the extrinsic base region by at least a first spacer of the asymmetrical sidewall spacers; and an emitter region on the semiconductor substrate and separated from the extrinsic base region by a second spacer of the asymmetrical sidewall spacers.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: March 19, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Alexander Derrickson, Vibhor Jain, Judson R. Holt, Jagar Singh, Mankyu Yang
  • Patent number: 11929542
    Abstract: System in package (SiP) modules are compact packages that include components such as processors, memory, sensors, and passive components on a single substrate. One low cost and compact way to integrate an antenna into a SiP module is to suspend an antenna in molding compound so that the antenna is embedded in the real estate of the molding compound layer. To embed the antenna, the molding compound is first deposited. A cavity can be cut in the molding compound to hold the antenna. The cavity can be filled with conductive material to form the antenna. Further molding compound can be deposited to cover the antenna and enclose the antenna in the molding compound layer. Ground structures can also be suspended in the molding compound. Such an embedded antenna can be particularly useful for radio applications.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: March 12, 2024
    Assignee: Analog Devices International Unlimited Company
    Inventor: Romulo Maggay
  • Patent number: 11908931
    Abstract: Provided is a monolithic metal-insulator transition device. The monolithic metal-insulator transition device includes a substrate including a driving region and a switching region, first and second source/drain regions on the driving region, a gate electrode between the first and second source/drain regions, an inlet well region formed adjacent to an upper surface of the substrate on the switching region, a control well region having a different conductivity type from the inlet well region between the inlet well region and a lower surface of the substrate, a first wiring electrically connecting the first source/drain region and the control well region, and a second wiring electrically connecting the second source/drain region and the inlet well region.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Tae Moon Roh, Hyun-Tak Kim, Sun Ae Kim
  • Patent number: 11908894
    Abstract: A method of making a deformable electronic device comprises forming a multilayer device structure comprising functional layers on a flexible substrate. At least one, some or all of the functional layers comprises a stack of 2D monolayers, and a number or proportion of misaligned interfaces within each stack of 2D monolayers is controlled to obtain a predetermined bending stiffness. Each of the misaligned interfaces comprises a twist angle and/or lattice mismatch between adjacent 2D monolayers. The functional layers may include electronically active layers and other layers having a dielectric, insulating, and/or protective function.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: February 20, 2024
    Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
    Inventors: Pinshane Huang, Arend van der Zande, Elif Ertekin, Edmund Han, Jaehyung Yu, Mohammad Abir Hossain
  • Patent number: 11894399
    Abstract: Hyperspectral resonant cavity imaging spectrometers and imaging systems incorporating the resonant cavity spectrometers are provided. The spectrometers include an array of photodetectors based on photosensitive semiconductor nanomembranes disposed between two dielectric spacers, each of the dielectric spacers having a thickness gradient along a lateral direction, such that the resonant cavity height differs for different photodetectors in the array.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Zhenqiang Ma, Zhenyang Xia, Ming Zhou, Qiaoqiang Gan, Zongfu Yu
  • Patent number: 11887972
    Abstract: A display device with a high luminance, a high contrast, and low power consumption is provided. The display device includes a transistor, a light-emitting element, a coloring layer, a phosphor layer, a first electrode, and a second electrode. The light-emitting element is electrically connected to the first electrode and the second electrode, the first electrode is electrically connected to the transistor, and the second electrode is positioned on the same plane as the first electrode. The coloring layer is positioned over the light-emitting element, the phosphor layer is positioned between the light-emitting element and the coloring layer, and the phosphor layer, the light-emitting element, and the coloring layer include a region in which they overlap with one another. The light-emitting element includes a light-emitting diode chip, and the phosphor layer has a function of emitting light of a complementary color of an emission color of the light-emitting element.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: January 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Kusunoki, Yosuke Tsukamoto, Kensuke Yoshizumi
  • Patent number: 11888038
    Abstract: An integrated circuit device includes a substrate having an active area therein, a bit line on the substrate, and a direct contact, which extends between the active area and the bit line and electrically couples the bit line to a portion of the active area. A spacer structure is also provided, which extends on sidewalls of the bit line and on sidewalls of the direct contact. A field passivation layer is provided, which extends between the sidewalls of the direct contact and the spacer structure. The spacer structure and the field passivation layer may include different materials, and the field passivation layer may directly contact the sidewalls of the direct contact. The field passivation layer can include nonstoichiometric silicon oxide SiOx, where 0.04?x?0.4, and may have a thickness of less than about 25 ?.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 30, 2024
    Inventor: Joonyoung Choi
  • Patent number: 11881685
    Abstract: An ion generation device includes a discharge electrode substrate, an induction electrode substrate, and an insulating resin. The discharge electrode substrate on which a discharge electrode is mounted and a first electrode connected to the discharge electrode is formed. The induction electrode substrate on which an induction electrode configured to generate a discharge between the induction electrode and the discharge electrode and a second electrode connected to the induction electrode are formed. The insulating resin is filled at least between the discharge electrode and the induction electrode. The insulating resin provides insulation between the discharge electrode and the induction electrode. The first electrode and the second electrode are disposed and face each other at least partially. The first electrode, the second electrode, and the insulating resin interposed between the first electrode and the second electrode form a capacitor.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 23, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Nobuyuki Ohe, Tetsuya Ezaki, Satoshi Okano
  • Patent number: 11876134
    Abstract: A semiconductor device includes a source region. A drain region has a first conductivity type and a second dopant concentration spaced apart from the source region. A first drift region is located between the source region and the drain region and has the first conductivity type and a first dopant concentration that is lower than the second dopant concentration of the drain region. An oxide structure includes a first portion on or over the first drift region and a tapered portion between the first portion and the drain region. A substrate surface extension is between the tapered portion and the drain region. A buffer region has the first conductivity type between the first drift region and the drain region and under the tapered portion of the oxide structure. The buffer region has a third dopant concentration between the second dopant concentration and the first dopant concentration.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: January 16, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Henry Litzmann Edwards
  • Patent number: 11862670
    Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: January 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Fu Lin, Tsung-Hao Yeh, Chih-Wei Hung
  • Patent number: 11862699
    Abstract: A semiconductor structure includes: a substrate with conductive contact regions; a bit line structure and an isolation wall located on a sidewall of the bit line structure, the isolation wall includes at least one isolation layer including a first isolation part close to the bit line structure and a second isolation part deviating from the same, the second isolation part has doped ions, such that it has a greater hardness than the first isolation part, or has a smaller dielectric constant than the first isolation part; and a capacitor contact hole, which exposes the conductive contact region, and has a top width greater than a bottom width in a direction parallel to an orientation of the bit line structure.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 2, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Jingwen Lu
  • Patent number: 11864469
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: January 2, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Ya-Sheng Feng
  • Patent number: 11855202
    Abstract: A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ching Wu, Po-Jen Wang
  • Patent number: 11843037
    Abstract: Provided are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a channel layer at least one of on or in the substrate, an insulation layer on the substrate, a ferroelectric layer on the insulation layer, a fixed charge layer on an interface between the insulation layer and the ferroelectric layer, the fixed charge layer including charges of a first polarity, and a gate on the ferroelectric layer.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: December 12, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dukhyun Choe, Jinseong Heo, Yunseong Lee, Sanghyun Jo
  • Patent number: 11829062
    Abstract: In a method of manufacturing a reflective mask, a photo resist layer is formed over a mask blank. The mask blank includes a substrate, a reflective multilayer on the substrate, a capping layer on the reflective multilayer, an absorber layer on the capping layer and a hard mask layer, and the absorber layer is made of Cr, CrO or CrON. The photo resist layer is patterned, the hard mask layer is patterned by using the patterned photo resist layer, the absorber layer is patterned by using the patterned hard mask layer, and an additional element is introduced into the patterned absorber layer to form a converted absorber layer.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: November 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Ta-Cheng Lien, Hsin-Chang Lee
  • Patent number: 11824058
    Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The method for forming a semiconductor device includes forming a first stack of channel structures that extends between a source terminal and a drain terminal of a first transistor in a first region of the semiconductor device. The first stack of channel structures includes a first channel structure and a second channel structure. The method further includes forming a first gate structure that wraps around the first stack of channel structures with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: November 21, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang