Abstract: A semiconductor device includes a substrate, an epitaxial structure over the substrate, a conductive structure, and a dielectric liner. The conductive structure extends from within the epitaxial structure to above the epitaxial structure. The dielectric liner extends along a sidewall of the conductive structure. The dielectric liner has a top end capped by the conductive structure.

Abstract: Provided is a semiconductor device including: a substrate containing a semiconductor material; an electrode provided on a substrate surface of the substrate, the electrode containing a metal material; and a mixed member provided on the substrate surface to be in contact with the electrode, the mixed member containing the semiconductor material and the metal material, in which a portion of the substrate surface is exposed at an end of the substrate.

Abstract: A display panel, a mask used for evaporation, a mask assembly and a manufacturing method thereof are provided. The display panel includes: a base substrate; and a display area and a peripheral area; wherein, the peripheral area is provided with two types of dummy sub-pixel units, each type of dummy sub-pixel unit includes a dummy light-emitting material layer and a dummy auxiliary light-emitting layer, wherein, a first structure layer of a first dummy light-emitting material layer and a first dummy auxiliary light-emitting layer is arranged in the same layer as a second structure layer of a second dummy light-emitting material layer and a second dummy auxiliary light-emitting layer, and at least one of a size and a shape of an orthographic projection of the second structure layer on the base substrate is different from that of an orthographic projection of the first structure layer on the base substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; removing the sacrificial layer to form a recess; forming a barrier layer and a free layer in the recess; forming a top electrode layer on the free layer; and patterning the top electrode layer and the free layer to form a second MTJ.

Abstract: Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

Abstract: A semiconductor device includes a drift region, a dielectric film, and an anti-type doping layer. The drift region has a first type conductivity. The anti-type doping layer is located between the drift region and the dielectric film, and has a second type conductivity opposite to the first type conductivity so as to change a current path of a current in the drift region, to thereby prevent the current from being influenced by the dielectric film. A method for manufacturing a semiconductor device and a method for reducing an influence of a dielectric film are also disclosed.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A method of making a semiconductor device, includes: providing a first dielectric layer; sequentially forming a first metal layer, a dummy capacitor dielectric layer, and a second metal layer over the first dielectric layer; and using a single mask layer with two patterns to simultaneously recess two portions of the second metal layer so as to define a metal thin film of a resistor and a top metal plate of a capacitor.

Abstract: Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

Abstract: A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: Provided is a synaptic device including a substrate, a channel layer on the substrate, a gate dielectric layer on the channel layer; and a gate electrode on the gate dielectric layer, wherein the gate dielectric layer includes a charge supply dielectric film and a piezoelectric film, wherein the charge supply dielectric film includes a metal oxide or metal sulfide, wherein the piezoelectric film includes a piezoelectric material that converts a pressure stimulation into an electrical signal, wherein accordance to a change in a signal applied to the gate electrode, a magnitude and aspect of a current flowing through the channel layer are changed.

Abstract: A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: An OLED display device includes a substrate, a first protection layer substrate, conductive lines extending substantially in a first direction, a second protection layer, a first electrode overlapping at least a part of the conductive lines, a pixel defining layer including an opening exposing at least a part of the first electrode, an organic light emission layer, and a second electrode. The opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction. A planar area of the first polygon is different from a planar area of the second polygon.

Abstract: Discussed is an electrode lead tack welding jig for a battery cell, and the jig including a jig body configured to support at least two battery cells, and a close contact guide unit provided to both ends of the jig body and configured to guide electrode leads of the at least two battery cells to come into close contact when tack welding is performed to the electrode leads by a laser.

Abstract: A light-emitting element which includes a plurality of light-emitting layers between a pair of electrodes and has low driving voltage and high emission efficiency is provided. A light-emitting element including first to third light-emitting layers between a cathode and an anode is provided. The first light-emitting layer includes a first phosphorescent material and a first electron-transport material; the second light-emitting layer includes a second phosphorescent material and a second electron-transport material; the third light-emitting layer includes a fluorescent material and a third electron-transport material; the first to third light-emitting elements are provided in contact with an electron-transport layer positioned on a cathode side; and a triplet excitation energy level of a material included in the electron-transport layer is lower than triplet excitation energy levels of the first electron-transport material and the second electron-transport material.

Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0?x1<1 is interposed between the first gate electrode and the AlGaN layer. A second p-type Alx2Ga1-x2N layer where 0?x2<1 is interposed between the second gate electrode and the AlGaN layer. The substrate is electrically insulated from all of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode. The bidirectional switch further includes a terminal used to connect the substrate to a fixed potential node. The terminal is connected to the substrate.

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

Abstract: A display device with a high luminance, a high contrast, and low power consumption is provided. The display device includes a transistor, a light-emitting element, a coloring layer, a phosphor layer, a first electrode, and a second electrode. The light-emitting element is electrically connected to the first electrode and the second electrode, the first electrode is electrically connected to the transistor, and the second electrode is positioned on the same plane as the first electrode. The coloring layer is positioned over the light-emitting element, the phosphor layer is positioned between the light-emitting element and the coloring layer, and the phosphor layer, the light-emitting element, and the coloring layer include a region in which they overlap with one another. The light-emitting element includes a light-emitting diode chip, and the phosphor layer has a function of emitting light of a complementary color of an emission color of the light-emitting element.