Patents Examined by Raj R Gupta
  • Patent number: 10651325
    Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: PSIQUANTUM CORP.
    Inventors: Faraz Najafi, Mark Thompson, Damien Bonneau, Joaquin Matres Abril
  • Patent number: 10651182
    Abstract: An embodiment includes a three dimensional (3D) memory that includes a NOR logic gate, wherein the NOR logic gate includes a ferroelectric based transistor. Other embodiments are addressed herein.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 12, 2020
    Assignee: Intel Corporation
    Inventors: Daniel H. Morris, Uygar E. Avci, Ian A. Young
  • Patent number: 10651424
    Abstract: Control of the emission characteristics of a light source in a light field display poses a significant benefit in the resulting 3D display quality for current and future technologies. A design system for microcavity OLEDs of any wavelength is detailed, which combines theoretical background with FDTD optimizations, permitting microcavity design of any OLED configuration. The resulting output profiles for microcavity OLEDs designed and fabricated with this method are compared to standard OLEDs and provide a reduction in spectral bandwidth, and a decrease in angular output.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: May 12, 2020
    Assignee: Avalon Holographics Inc.
    Inventors: Jordan Peckham, Jennifer Campbell, Jiaqi Cheng
  • Patent number: 10651356
    Abstract: A light-emitting component includes at least two radiation-emitting semiconductor chips of a first type configured to emit electromagnetic radiation during operation, and a light exit surface at a light exit side of the light-emitting component, wherein each of the radiation-emitting semiconductor chips of the first type includes a semiconductor layer sequence with a stacking direction, the stacking direction of each radiation-emitting semiconductor chip of the first type is parallel to the light exit surface of the component, and all the semiconductor chips of the first type are arranged directly below the light exit surface.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: May 12, 2020
    Assignee: OSRAM OLED GmbH
    Inventor: Siegfried Herrmann
  • Patent number: 10648644
    Abstract: A cover for a light source for use in a lamp or luminaire. An outer surface of the cover, opposite the light source, comprises a rounded shape and includes a protrusion extending from the cover. The protrusion extends substantially in a light emission direction and is shaped the protrusion to direct light emitted from the light source in a desired direction.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: May 12, 2020
    Assignee: BRIDGELUX INC.
    Inventor: Xiaolu Chen
  • Patent number: 10649289
    Abstract: An array substrate, a display panel and a display device are provided. The array substrate includes a plurality of signal lines each connected to a plurality of subpixel units. The plurality of signal lines includes first signal lines. The plurality of subpixel units connected to each first signal line is divided into at least two groups each including at least one subpixel unit. An overlapping area between a common electrode and a pixel electrode of each subpixel unit in the group of subpixel units adjacent to a signal input end of the first signal line is larger than an overlapping area between a common electrode and a pixel electrode of each subpixel unit in the group of subpixel units away from the signal input end of the first signal line.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 12, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Sha Liu, Zhaokun Yang, Xiang Feng, Qiang Zhang, Xiao Sun
  • Patent number: 10644153
    Abstract: A fin field effect transistor (FinFET) is provided. The FinFET includes a substrate, a gate stack, and a filter layer, and strain layers. The substrate has a semiconductor fin. The gate stack is disposed across the semiconductor fin. The gate stack includes a gate dielectric layer, a work function layer and a metal filling layer. The gate dielectric layer is disposed on the semiconductor fin. The work function layer is disposed on the gate dielectric layer. The metal filling layer is over the work function layer. The filter layer is disposed between the work function layer and the metal filling layer to prevent or decrease penetration of diffusion atoms. The strain layers are beside the gate stack. A material of the filter layer is different from a material of the work function layer and a material of the metal filling layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chang Wei, Chia-Lin Hsu, Hsien-Ming Lee, Ji-Cheng Chen
  • Patent number: 10634963
    Abstract: A thin-film transistor array including an insulating substrate, gate lines formed on the insulating substrate, source lines formed on the insulating substrate, and transistors each being formed on the insulating substrate at a position corresponding to a respective intersection of the gate lines and the source lines, and formed in a matrix including pixels in rows and columns, each of the transistors including a gate electrode connected to each of the gate lines, a source electrode connected to each of the source lines, a drain electrode, and a pixel electrode connected to the drain electrode. Each of the source lines is connected to a column of pixels, and each of the gate lines includes a first portion connected to a predetermined number of pixels in a row and a second portion connected to pixels in an adjacent row.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 28, 2020
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventor: Mamoru Ishizaki
  • Patent number: 10636816
    Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: April 28, 2020
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Jilei Gao, Xuebing Jiang, Songmei Sun, Peng Wu, Jian Zhao, Yang Zhang, Mo Chen
  • Patent number: 10636660
    Abstract: To manufacture a super-junction (SJ) layer of a SJ device, an epitaxial (epi) layer having a first conductivity type may be formed on an underlying layer, which may be formed from a wide-bandgap material. A first mask may then be formed onto a first portion of the epi layer, and a first set of SJ pillars may be selectively implanted into a second portion of the epi layer exposed by the first mask. Then, a second mask may be formed on the second portion of the epi layer that is self-aligned relative to the first mask. After removing the first mask, a second set of SJ pillars may be selectively implanted into the first portion of the epi layer. Removing the second mask may then yield the SJ layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 28, 2020
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Reza Ghandi, Alexander Viktorovich Bolotnikov, Peter Almern Losee, David Alan Lilienfeld
  • Patent number: 10629840
    Abstract: The present invention provides an organic optoelectronic device and a method for manufacturing the same, in which laser scanning is used to form the electrical connection between the second electrode layer and the contact electrode layer. The present invention can effectively decrease the frequency of replacement of metal masks, significantly shorten the time required for replacing the metal masks, and reduce the down time due to the replacement of metal masks. In addition, the organic optoelectronic device can have a large active area due to the narrow border of the electrical connection formed by the laser scanning.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: April 21, 2020
    Inventors: Sheng-Yang Huang, Ching-Yan Chao, Cheng-Hao Chang, Feng-Wen Yen
  • Patent number: 10615275
    Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: April 7, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Patent number: 10615316
    Abstract: A lighting apparatus is presented. The lighting apparatus includes a semiconductor light source capable of producing blue light of high power density, the semiconductor light source radiationally coupled to a phosphor of formula I in a monolithic form selected from single crystal and ceramic, Ax (M, Mn)Fy (I) where A is Li, Na, K, Rb, Cs, or a combination thereof, M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof, x is an absolute value of a charge of an [MFy] ion; and y is 5, 6, or 7.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: April 7, 2020
    Assignee: CURRENT LIGHTING SOLUTIONS, LLC
    Inventors: James Edward Murphy, Sam Joseph Camardello
  • Patent number: 10600847
    Abstract: An OLED display device includes a substrate, a first protection layer substrate, conductive lines extending substantially in a first direction, a second protection layer, a first electrode overlapping at least a part of the conductive lines, a pixel defining layer including an opening exposing at least a part of the first electrode, an organic light emission layer, and a second electrode. The opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction. A planar area of the first polygon is different from a planar area of the second polygon.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: March 24, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sangmin Hong, Heeseong Jeong
  • Patent number: 10600785
    Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Seid Hadi Rasouli, Michael Joseph Brunolli, Christine Sung-An Hau-Riege, Mickael Malabry, Sucheta Kumar Harish, Prathiba Balasubramanian, Kamesh Medisetti, Nikolay Bomshtein, Animesh Datta, Ohsang Kwon
  • Patent number: 10580870
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Fumikazu Imai
  • Patent number: 10580646
    Abstract: An epitaxial substrate for semiconductor elements is provided which suppresses the occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer adjacent to the free-standing substrate; a channel layer adjacent to the buffer layer; and a barrier layer provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of AlpGa1-pN (0.7?p?1) and suppresses diffusion of Zn from the free-standing substrate into the channel layer.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: March 3, 2020
    Assignee: NGK INSULATORS, LTD.
    Inventors: Mikiya Ichimura, Sota Maehara, Yoshitaka Kuraoka
  • Patent number: 10566332
    Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kuo-Chen Wang, Shih-Fan Kuan, Lars Heineck, Sanh D. Tang
  • Patent number: 10557081
    Abstract: The present invention relates to light-converting materials which comprise semiconductor nanoparticles and an unactivated crystalline material, where the semiconductor nanoparticles are located on the surface of the unactivated crystalline material. The present invention furthermore relates to the use of the light-converting material in a light source. The present invention furthermore relates to a light-converting mixture, to a light source, to a lighting unit which contains the light-converting material according to the invention, and to a process for the production of the light source.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 11, 2020
    Assignee: Merck Patent GmbH
    Inventors: Norbert Stenzel, Andrea Opolka, Bernhard Rieger, Stefan Tews
  • Patent number: 10559775
    Abstract: An organic EL display device according to an embodiment of the present invention includes: a base material; a plurality of pixels; a lower electrode which each of the plurality of pixels is provided with; an organic insulation layer which sections the plurality of pixels; an organic material layer which is disposed on the lower electrode and the organic insulation layer, and includes a plurality of layers; and an upper electrode on the organic material layer. A level difference part is positioned on an upper surface of the organic insulation layer, a first layer included in the organic material layer is divided at the level difference part, or has a thin part being thinner at the level difference part than at a position at which the first layer faces the lower electrode, and a second layer included in the organic material layer is not divided at the level difference part.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 11, 2020
    Assignee: Japan Display Inc.
    Inventor: Asami Sakamoto