Patents Examined by Raj R Gupta
  • Patent number: 10557081
    Abstract: The present invention relates to light-converting materials which comprise semiconductor nanoparticles and an unactivated crystalline material, where the semiconductor nanoparticles are located on the surface of the unactivated crystalline material. The present invention furthermore relates to the use of the light-converting material in a light source. The present invention furthermore relates to a light-converting mixture, to a light source, to a lighting unit which contains the light-converting material according to the invention, and to a process for the production of the light source.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: February 11, 2020
    Assignee: Merck Patent GmbH
    Inventors: Norbert Stenzel, Andrea Opolka, Bernhard Rieger, Stefan Tews
  • Patent number: 10559775
    Abstract: An organic EL display device according to an embodiment of the present invention includes: a base material; a plurality of pixels; a lower electrode which each of the plurality of pixels is provided with; an organic insulation layer which sections the plurality of pixels; an organic material layer which is disposed on the lower electrode and the organic insulation layer, and includes a plurality of layers; and an upper electrode on the organic material layer. A level difference part is positioned on an upper surface of the organic insulation layer, a first layer included in the organic material layer is divided at the level difference part, or has a thin part being thinner at the level difference part than at a position at which the first layer faces the lower electrode, and a second layer included in the organic material layer is not divided at the level difference part.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: February 11, 2020
    Assignee: Japan Display Inc.
    Inventor: Asami Sakamoto
  • Patent number: 10553668
    Abstract: A display panel may include a detection line overlapped with a non-display region, detection pads connected to the detection line, and an input line connecting an input pad of the detection pads to the detection line. The detection line may include a first portion, which is provided at a level different from a level of the input line and includes an end connected to the input line through a first contact hole in a first contact region, and a second portion, which is provided at a level different from the level of the first portion and is connected to the first portion through a second contact hole in a second contact region. A distance between the first and second portions in a non-contact region may be less than a distance between the first contact hole and the second portion.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 4, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonse Lee, Hyunwoong Kim, Joong-Soo Moon, Ae Shin, Ji-eun Lee, Kwangmin Kim, Seungkyu Lee
  • Patent number: 10553587
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: February 4, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10553726
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Patent number: 10546988
    Abstract: A light emitting device includes a light emitting element; a sub-mount including a sub-mount substrate with a front surface on which the light emitting element is disposed, and a back surface electrode disposed in a back surface that is on a back side of the front surface of the sub-mount substrate; a main-mount in which the sub-mount is disposed, the main-mount including a front surface metal pattern including a wiring electrode bonded to the back surface electrode via solder. The front surface metal pattern has a slit, in a plan view, at a position away from a disposition region in which the sub-mount is disposed.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: January 28, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Masahiro Hayashi, Tetsuya Kamada, Takashi Kuwaharada, Kiyomi Hagihara, Toshikazu Shimokatano, Shigeo Hayashi, Hiroki Shirozono, Hideaki Usukubo
  • Patent number: 10522655
    Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: December 31, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: George Robert Mulfinger, Ryan Sporer, Rick J. Carter, Peter Baars, Hans-Jürgen Thees, Jan Höntschel
  • Patent number: 10510684
    Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Szu-Wei Lu, Jing-Cheng Lin
  • Patent number: 10505141
    Abstract: A flexible display substrate, a manufacturing method thereof and a flexible display device are provided. The flexible display substrate includes a flexible substrate and a cathode layer arranged on the flexible substrate and provided with at least one gap.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: December 10, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Xiaobo Du
  • Patent number: 10504977
    Abstract: An organic light-emitting circuit structure having a temperature function includes an organic light-emitting diode which has an anode and a cathode opposite to each other; a driving transistor including a first electrode and a second electrode; the first electrode is a source electrode, the second electrode is a drain electrode; or, the first electrode is the drain electrode, the second electrode is the source electrode; a temperature sensitive resistor, which is electrically connected between the driving transistor and the light-emitting device or between the driving transistor and the voltage source. The temperature sensitive resistor increases a resistance value at sensing a temperature increase or decreases the resistance value at sensing a temperature decrease. As a result a current through the organic light-emitting diode stays compensated and stable, thereby ensuring that the organic light-emitting diode keeps emitting light normally under various temperature conditions.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 10, 2019
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Zhiyong Xiong, Duzen Peng, Jianjie Zhu
  • Patent number: 10505147
    Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: December 10, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Jun Seok Lee
  • Patent number: 10504878
    Abstract: Disclosed is an LED module assembly for a display including a first LED module and a second LED module. The first LED module includes a first unit substrate, a plurality of LED chips mounted on the first unit substrate to form a plurality of pixels, and a first light absorbing layer formed on the first unit substrate. The second LED module includes a second unit substrate, a plurality of LED chips mounted on the second unit substrate to form a plurality of pixels, and a second light absorbing layer formed on the second unit substrate. The first unit substrate and the second unit substrate are laterally connected to each other. Each of the first light absorbing layer and the second light absorbing layer includes a plurality of valleys formed between the plurality of pixels.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 10, 2019
    Assignee: LUMENS CO., LTD.
    Inventors: Chunki Min, Keunoh Kim, Huikyeong Noh, Kyungmin Cho
  • Patent number: 10493590
    Abstract: Values are selected for a plurality of controllable parameters of a chemical mechanical polishing system that includes a carrier head with a plurality of zones to apply independently controllable pressures on a substrate. Data is stored relating variation in removal profile on a front surface of the substrate to variation in the controllable parameters, the data including removal at a plurality of positions on the front surface of the substrate, there being a greater number of positions than chambers. A value is determined for each parameter of the plurality of controllable parameters to minimize a difference between a target removal profile and an expected removal profile calculated from the data relating variation in removal profile on a front surface of the substrate to variation in the parameters. The value for each parameter of the plurality of controllable parameters is stored.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 3, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Huanbo Zhang, Garrett Ho Yee Sin, King Yi Heung, Nathan Bohannon, Qing Zhang
  • Patent number: 10475823
    Abstract: The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate arranges a connection electrode (83) that connects two dual gate TFTs in a third metal layer to prevent the design rules of a connection electrode and a second metal layer of the prior art techniques from being narrowed due to the connection electrode being collectively present on the second metal layer with signal lines of a data line and a voltage supply line so as to facilitate increase of an aperture ratio and definition of a display panel. The present invention provides a TFT substrate structure, which has a simple structure and possesses a high aperture ratio and high definition.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 12, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Longqiang Shi, Baixiang Han
  • Patent number: 10461079
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 10453805
    Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 22, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Patent number: 10453955
    Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: October 22, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wai Ng, Ruey-Hsin Liu, Jun Cai, Hsueh-Liang Chou, Chi-Chih Chen
  • Patent number: 10446678
    Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: October 15, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Patent number: 10438948
    Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chen-Han Wang, Chun-Hsiung Lin
  • Patent number: 10439165
    Abstract: An organic light emitting diode display is disclosed in which a flow control pattern of an organic protective layer is disposed to implement a thin bezel. In an active area and a bezel area defined on a substrate, the flow control pattern disposed reduces the flow of a protective layer so as to minimize area size of the bezel area.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 8, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: JinHwan Kim, WooChan Kim, Hyunchul Um