Abstract: A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

Abstract: An OLED display device includes a substrate, a first protection layer substrate, conductive lines extending substantially in a first direction, a second protection layer, a first electrode overlapping at least a part of the conductive lines, a pixel defining layer including an opening exposing at least a part of the first electrode, an organic light emission layer, and a second electrode. The opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction. A planar area of the first polygon is different from a planar area of the second polygon.

Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.

Abstract: Discussed is an electrode lead tack welding jig for a battery cell, and the jig including a jig body configured to support at least two battery cells, and a close contact guide unit provided to both ends of the jig body and configured to guide electrode leads of the at least two battery cells to come into close contact when tack welding is performed to the electrode leads by a laser.

Abstract: A GaN layer is formed over the substrate. An AlGaN layer is formed on the GaN layer. A first source electrode, a first gate electrode, a second gate electrode, and a second source electrode are formed on or over the AlGaN layer. A first p-type Alx1Ga1-x1N layer where 0?x1<1 is interposed between the first gate electrode and the AlGaN layer. A second p-type Alx2Ga1-x2N layer where 0?x2<1 is interposed between the second gate electrode and the AlGaN layer. The substrate is electrically insulated from all of the first source electrode, the second source electrode, the first gate electrode, and the second gate electrode. The bidirectional switch further includes a terminal used to connect the substrate to a fixed potential node. The terminal is connected to the substrate.

Abstract: A light-emitting element which includes a plurality of light-emitting layers between a pair of electrodes and has low driving voltage and high emission efficiency is provided. A light-emitting element including first to third light-emitting layers between a cathode and an anode is provided. The first light-emitting layer includes a first phosphorescent material and a first electron-transport material; the second light-emitting layer includes a second phosphorescent material and a second electron-transport material; the third light-emitting layer includes a fluorescent material and a third electron-transport material; the first to third light-emitting elements are provided in contact with an electron-transport layer positioned on a cathode side; and a triplet excitation energy level of a material included in the electron-transport layer is lower than triplet excitation energy levels of the first electron-transport material and the second electron-transport material.

Abstract: A method for patterning a substrate in which a patterned photoresist structure can be formed on the substrate, the patterned photoresist structure having a sidewall. A conformal layer of spacer material can be deposited on the sidewall. The patterned photoresist structure can then be removed from the substrate, leaving behind the spacer material. Then, the substrate can be directionally etched using the sidewall spacer as an etch mask to form the substrate having a target critical dimension.

Abstract: A display device with a high luminance, a high contrast, and low power consumption is provided. The display device includes a transistor, a light-emitting element, a coloring layer, a phosphor layer, a first electrode, and a second electrode. The light-emitting element is electrically connected to the first electrode and the second electrode, the first electrode is electrically connected to the transistor, and the second electrode is positioned on the same plane as the first electrode. The coloring layer is positioned over the light-emitting element, the phosphor layer is positioned between the light-emitting element and the coloring layer, and the phosphor layer, the light-emitting element, and the coloring layer include a region in which they overlap with one another. The light-emitting element includes a light-emitting diode chip, and the phosphor layer has a function of emitting light of a complementary color of an emission color of the light-emitting element.

Abstract: A laminated glass structure for an electronic device includes: a core glass layer having a first coefficient of thermal expansion (CTE); and a plurality of clad glass layers, each having a CTE that is lower than or equal to the first CTE of the core glass layer. A first of the clad glass layers is laminated to a first surface of the core glass layer and a second of the clad layers is laminated to a second surface of the core glass layer. Further, the total thickness of the core glass layer and the clad glass layers ranges from about 0.1 mm to about 3 mm. In addition, each of the first of the clad layers and the core glass layer comprises a loss tangent of 0.006 or less for signals having a frequency of 1 GHz to about 100 GHz.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: A silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) structure is provided, including a substrate layer; a buried oxide layer which is arranged on an upper surface of the substrate layer and is made of SiO2; an active zone which is arranged on an upper surface of the buried oxide layer; a source electrode and a drain electrode which are arranged on an upper surface of the active zone; a gate dielectric layer which is arranged between the source electrode and the drain electrode; a gate electrode which is provided in the gate dielectric layer; and a heat conduction column which penetrates through the buried oxide layer, and its top wall is in contact with the active zone. The heat conduction column dissipates heat in the active zone, resulting in a lattice temperature of the active zone will not increase extremely and avoiding a decrease of a current of the drain electrode.

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

Abstract: A display device with a high luminance, a high contrast, and low power consumption is provided. The display device includes a transistor, a light-emitting element, a coloring layer, a phosphor layer, a first electrode, and a second electrode. The light-emitting element is electrically connected to the first electrode and the second electrode, the first electrode is electrically connected to the transistor, and the second electrode is positioned on the same plane as the first electrode. The coloring layer is positioned over the light-emitting element, the phosphor layer is positioned between the light-emitting element and the coloring layer, and the phosphor layer, the light-emitting element, and the coloring layer include a region in which they overlap with one another. The light-emitting element includes a light-emitting diode chip, and the phosphor layer has a function of emitting light of a complementary color of an emission color of the light-emitting element.

Abstract: A semiconductor epitaxy structure includes a silicon carbide substrate, a nucleation layer, a gallium nitride buffer layer, and a stacked structure. The nucleation layer is formed on the silicon carbide substrate, the gallium nitride buffer layer is disposed on the nucleation layer, and the stacked structure is formed between the nucleation layer and the gallium nitride buffer layer. The stacked structure includes: a plurality of silicon nitride (SiNx) layers and a plurality of aluminum gallium nitride (AlxGa1-xN) layers alternately stacked, wherein the first layer of the plurality of silicon nitride layers is in direct contact with the nucleation layer.

Abstract: A method of using a processing apparatus that includes a holding unit with a rotatable chuck table for holding a workpiece; a processing unit for processing the workpiece; a camera for imaging the workpiece that is movable in an indexing feed direction; and a control unit for controlling the components. The method includes forming a linear processed mark in the workpiece, and then moving the chuck table to an imaging zone, where the camera images the processed mark. The method further includes calculating correction values or a correction angle, and carrying out processing feed of the chuck table in the imaging zone under a condition in which the camera has been corrected in position in the Y-axis direction based on the correction values or the chuck table has been rotated by the correction angle.

Abstract: The present invention provides a monolithic LED array precursor comprising a plurality of LED structures, an LED device comprising the monolithic LED array, and a method of manufacture thereof. In particular, the present disclosure provides a monolithic LED array having improved light emission.

Abstract: A semiconductor device includes a first diffusion region of a first type with embedded therein, a second and a third diffusion region of a second type different from the first type. The second and third diffusion regions are more doped than the first region. The second and third diffusion regions are each connected to a respective contact. A dielectric layer covers at least an edge of the second and third diffusion regions, and the region in between the second and third diffusion regions. A piezoelectric layer is disposed on, over, adjacent to or in contact with the dielectric layer. A first structure is in a first soft ferromagnetic material and is arranged to perform mechanical stress on the piezoelectric layer in response to a magnetic field.

Abstract: A semiconductor device includes a semiconductor substrate, a trench, and a gate structure. The trench is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The gate structure includes a gate electrode, a first gate oxide layer, and a second gate oxide layer. A first portion of the gate electrode is disposed in the trench, and a second portion of the gate electrode is disposed outside the trench. The first gate oxide layer is disposed between the gate electrode and the semiconductor substrate. At least a portion of the first gate oxide layer is disposed in the trench. The second gate oxide layer is disposed between the second portion of the gate electrode and the semiconductor substrate in a vertical direction. A thickness of the second gate oxide layer is greater than a thickness of the first gate oxide layer.

Abstract: Surface supported quantum wells with a confined surface state capture and stably confine neutral atoms and molecules in a nanometer precise environment. Depending on the physico-chemical conditions in the capturing process, the degree of occupancy, the temperature of the solid substrate, and/or the history of external stimuli like electromagnetic field pulses, these atoms, molecules or clusters assume unique configurations. The atoms or molecules are able to remain coupled to the quantum-well specific electronic state in the confinement and as such exhibit local and delocalized quantum entanglement. The capturing potential arises from the superposition of Pauli repulsion between the captured object and the quantum well-specific confined electronic state. This occurs within on-surface atomic or supramolecular assemblies or surface supported coordination or covalent networks.

Abstract: A light emitting diode device and a manufacturing method thereof, a display panel, and a display apparatus are provided. The light emitting diode device includes a quantum dot light emitting layer and a hole transport layer on a side of the quantum dot light emitting layer. The hole transport layer includes a perovskite material and an organic hole transport material. The high carrier mobility of the perovskite material can improve the carrier transport performance of the hole transport layer.