Patents Examined by Raj R Gupta
  • Patent number: 10429702
    Abstract: The present disclosure provides a pixel structure, an array substrate and a display apparatus, aiming at achieving good display effects in all viewing directions and improved viewing angles. The pixel structure comprises a plurality of transparent electrodes, which are arranged in columns and each transparent electrode corresponds to a subpixel. Each transparent electrode comprises at least two sub-electrode portions, and each sub-electrode portion is provided with a plurality of slits.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: October 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Rui Wang, Haijun Qiu, Fei Shang, Jaikwang Kim, Shaoru Li, Rikun Jiang
  • Patent number: 10427932
    Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: October 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: John Charles Ehmke, Virgil Cotoco Ararao
  • Patent number: 10424493
    Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: September 24, 2019
    Assignee: Apple Inc.
    Inventors: Hsin-Hua Hu, Andreas Bibl, John A. Higginson
  • Patent number: 10424643
    Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 24, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Andrew D. Koehler, Francis J. Kub, Travis J. Anderson, Tatyana I. Feygelson, Marko J. Tadjer, Lunet E. Luna
  • Patent number: 10424671
    Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: September 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Hidekazu Miyairi, Akihisa Shimomura, Atsushi Hirose
  • Patent number: 10418458
    Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: September 17, 2019
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Chih-Ming Sun, Hsin-Hui Hsu, Ming-Han Tsai
  • Patent number: 10396274
    Abstract: A method of manufacturing a spintronics element from laminated layers. The method includes (a) forming a plurality of laminated layers in manufacturing equipment, (b) forming a wafer in the manufacturing equipment, including applying a protection layer directly on a non-magnetic uppermost layer of the laminated layers so that the protection layer prevents alteration of characteristics of the uppermost layer, and (c) exposing the wafer, outside of the manufacturing equipment, to an atmosphere that includes H2O having a partial pressure in the atmosphere equal to or larger than 10?4 Pa.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: August 27, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Ohno, Tetsuo Endo
  • Patent number: 10396089
    Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 27, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Tsutomu Okazaki, Daisuke Okada, Kyoya Nitta, Toshihiro Tanaka, Akira Kato, Toshikazu Matsui, Yasushi Ishii, Digh Hisamoto, Kan Yasui
  • Patent number: 10388795
    Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ramachandra Divakaruni
  • Patent number: 10372096
    Abstract: A method, user interface control arrangement, and a computer program product for controlling a stationary user interface in an industrial process control system as well as to such a process control system. The user interface control arrangement obtains a first live video stream from a video camera monitoring an industrial process at a first location, obtains a process control view for the first location, overlays the process control view on the first live video stream and displays the first live video stream with the overlaid process control view on a display of the user interface.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 6, 2019
    Assignee: ABB Schweiz AG
    Inventor: Torbjörn Ottosson
  • Patent number: 10356196
    Abstract: A proxy device management apparatus includes: an attribute information storage that stores attribute information obtained from a management target device and information indicating a reception time of the attribute information; and a processor that performs a first operation or a second operation according to a difference between the reception time of the attribute information and a reception time of an obtaining request of the attribute information when the proxy device management apparatus receives the obtaining request from a device management apparatus. The first operation includes transmitting the attribute information stored in the attribute information storage to the device management apparatus. The second operation includes obtaining the attribute information corresponding to the obtaining request from the management target device and transmitting the obtained attribute information to the device management apparatus.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: July 16, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Yusuke Ejiri, Takeshi Fujiwara
  • Patent number: 10351418
    Abstract: An embodiment method includes forming a first plurality of bond pads on a device substrate, depositing a spacer layer over and extending along sidewalls of the first plurality of bond pads, and etching the spacer layer to remove lateral portions of the spacer layer and form spacers on sidewalls of the first plurality of bond pads. The method further includes bonding a cap substrate including a second plurality of bond pads to the device substrate by bonding the first plurality of bond pads to the second plurality of bond pads.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Ming Chen, Ping-Yin Liu, Chung-Yi Yu, Yeur-Luen Tu
  • Patent number: 10355233
    Abstract: The organic light-emitting diode (1) has a first electrode (21) with a first electric conductivity and a second electrode (22) with a second lower electric conductivity. An organic layer stack (4) for generating light is located between the electrodes (21, 22). The light-emitting diode (1) further comprises a current distribution layer (3) with a third high electric conductivity. When seen in a plan view, multiple contact regions (33) are located outside of an outer contour line (40) of the layer stack (4). The second electrode (22) and the current distribution layer (3) contact each other in the contact regions (33). In a current blocking region (34), the current distribution layer (3) is located entirely within the contour line (40) such that the second electrode (22) is electrically disconnected from the current distribution layer (3).
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: July 16, 2019
    Assignee: OSRAM OLED GMBH
    Inventors: Erwin Lang, Arne Fleissner, Andrew Ingle
  • Patent number: 10345659
    Abstract: The present disclosure provides an array substrate, the array substrate includes a plurality of array blocks arranged at intervals, wherein each array block includes a plurality of sub-array substrates arranged at intervals, at least one of a periphery of the array substrate, a periphery of the array block, and a periphery of the display area of the sub-array substrate is arranged with an electrostatic protection structure, the electrostatic protection structure is a transparent metal oxide wire, or a metal wire and a transparent conductive metal oxide wire arranged in layers. The existence of the electrostatic protection structure can effectively shield the outside static electricity. The disclosure also provides a liquid crystal display panel adopting the array substrate.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 9, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuanfu Liu
  • Patent number: 10347701
    Abstract: An organic light-emitting display panel, a display device, and an organic light-emitting display motherboard are provided. The organic light-emitting display panel includes a base substrate, a metal wire, a first insulation layer, and a conductive portion. The metal wire has an upper surface opposing to the base substrate. A material of the metal wire includes a first metal. The first insulation layer covers the upper surface of the metal wire and includes at least one hollow portion penetrating through the first insulation layer and exposing a portion of the upper surface of the metal wire. The conductive portion is electrically connected to the metal wire, and is not overlapped with the at least one hollow portion. A work function of a material of the conductive portion is G1, a work function of metal silver is G2, a work function of the first metal is G3, and G1>G2>G3.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: July 9, 2019
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Shui He, Yingteng Zhai, Yongxiang Lin, Hong Lin, Yong Yuan, Zaiwen Zhu, Qitai Ji
  • Patent number: 10347765
    Abstract: A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Xin Miao, Tenko Yamashita
  • Patent number: 10340480
    Abstract: Control of the emission characteristics of a light source in a light field display poses a significant benefit in the resulting 3D display quality for current and future technologies. A design system for microcavity OLEDs of any wavelength is detailed, which combines theoretical background with FDTD optimizations, permitting microcavity design of any OLED configuration. The resulting output profiles for microcavity OLEDs designed and fabricated with this method are compared to standard OLEDs and provide a reduction in spectral bandwidth, and a decrease in angular output.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: July 2, 2019
    Assignee: Avalon Holographics Inc.
    Inventor: Jordan Peckham
  • Patent number: 10333732
    Abstract: The invention relates to an arrangement for controlling electronically controllable devices and systems in public and private buildings and a method for controlling electronically controlling devices and systems in public and private buildings. Thus, the arrangements and methods for building automation are improved so that a user can generate combined control routines which comply with his wishes without prior knowledge of the effect of the individual control commands. Furthermore, the control routines are proposed to the user upon request by the user.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 25, 2019
    Assignee: iHaus AG
    Inventors: Robert Klug, Dieter Meiller, Hans Martin Roth
  • Patent number: 10325814
    Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 18, 2019
    Assignee: Intel Corporation
    Inventors: Paul A. Nyhus, Swaminathan Sivakumar
  • Patent number: 10312175
    Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 4, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Andrew D. Koehler, Francis J. Kub, Travis J. Anderson, Tatyana I. Feygelson, Marko J. Tadjer, Lunet E. Luna