Abstract: A method for fabricating semiconductor device includes the steps of: forming a first inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the first IMD layer; forming a bottom electrode layer and a pinned layer on the first IMD layer; forming a sacrificial layer on the pinned layer; patterning the sacrificial layer, the pinned layer, and the bottom electrode layer to form a first magnetic tunneling junction (MTJ); forming a second IMD layer around the first MTJ; and removing the sacrificial layer.

Abstract: A display device includes a substrate, an emission layer provided on the substrate and a reflective layer provided on the emission layer. The emission layer has an emission region that emits light, the reflective layer has a first opening, the emission region overlaps the first opening in a direction perpendicular to an upper surface of the substrate and a first width of the emission region is smaller than a second width of the first opening.

Abstract: An OLED display device includes a substrate, a first protection layer substrate, conductive lines extending substantially in a first direction, a second protection layer, a first electrode overlapping at least a part of the conductive lines, a pixel defining layer including an opening exposing at least a part of the first electrode, an organic light emission layer, and a second electrode. The opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction. A planar area of the first polygon is different from a planar area of the second polygon.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a first conductive layer on a first substrate and a second conductive layer on a second substrate. A bonding structure is disposed between the first conductive layer and the second conductive layer. A support structure is disposed between the first substrate and the second substrate. A passivation layer covers a bottom surface of the first conductive layer and has a lower surface facing an uppermost surface of the support structure.

Abstract: Integrated circuit structures, arrangements, and manufacturing processes are discussed herein. In one example, a method of forming a transistor structure includes forming a dielectric layer onto a gate element and forming a corrugated surface into the dielectric layer using at least an atomic layer etching (ALE) process to remove portions of the dielectric layer. The method also includes forming a semiconductor layer onto the corrugated surface and forming a source element and a drain element onto the semiconductor layer.

Abstract: A semiconductor device includes an active region, a gate ring region surrounding a periphery of the active region, and a source ring region surrounding a periphery of the gate ring region. The semiconductor device has a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, and a second electrode. The semiconductor device has, in the active region, first semiconductor regions of the first conductivity type, a gate insulating film, first gate electrodes, an interlayer insulating film and a first first-electrode, and has, in the source ring region, a third semiconductor region and a second first-electrode. In the source ring region, a second semiconductor region of the first or second conductivity type is provided at a bottom of the third semiconductor region, directly below the second first-electrode in a depth direction of the semiconductor device.

Abstract: A light emitting diode includes a first conductivity type semiconductor material region, an active region located over the first conductivity type semiconductor material region, a second conductivity type semiconductor material layer located over the active region, a first layer containing at least one of nickel or gold located over the second conductivity type semiconductor material layer, a reflective top contact electrode located over the first layer, a dielectric material layer located over the top contact electrode and containing an opening, and a reflector located over the dielectric material layer and contacting the top contact electrode through the opening in the dielectric material layer.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric.

Abstract: Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.

Abstract: A display device having a light-emitting device is provided. The display device can include a buffer insulating layer disposed on a path of light emitted from the light-emitting device. The buffer insulating layer can have a stacked structure of a first buffer insulating layer having the refractive index which decreases in a direction away from the light-emitting device, and a second buffer insulating layer having the refractive index which increases in a direction away from the light-emitting device. Thus, in the display device, the unintended constructive and destructive interference of the light emitted from the light-emitting device can be prevented. Therefore, in the display device, the luminous efficacy can be increased, and the variation of color coordinates can be prevented.

Abstract: An organic thin-film transistor includes an insulating substrate, a capacitor electrode formed on the insulating substrate, a first insulating layer covering the capacitor electrode, a gate electrode formed on the first insulating layer, a second insulating layer covering the gate electrode and the capacitor electrode, a source electrode formed on the second insulating layer, a drain electrode formed on the second insulating layer, and a semiconductor layer formed on the second insulating layer in a portion between the source electrode and the drain electrode and including an organic semiconductor material.

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

Abstract: The present application disclosed a conducting layer-dielectric layer-conducting layer (CDC) laminate structure and test method for detecting defects of an inter-metal dielectric layer. The laminate structure comprises: a dielectric layer formed on a substrate; a first conducting layer formed at a first side of the dielectric layer, wherein the first conducting layer includes a first metal region and at least one first opening in the first metal region; and a second conducting layer formed at a second side of the dielectric layer opposite to the first conducting layer such that the second conducting layer is separated from the first conducting layer by the dielectric layer, wherein the second conducting layer includes a second metal region and a plurality of second openings in the second metal region.

Abstract: A MEMS microphone includes a substrate defining a cavity, a diaphragm being spaced apart from the substrate, covering the cavity, and being configured to generate a displacement thereof in response to an applied acoustic pressure, an anchor extending from an end portion of the diaphragm, the anchor including a lower surface in contact with an upper surface of the substrate to support the diaphragm, a back plate disposed over the diaphragm, the back plate being spaced apart from the diaphragm such that an air gap is maintained between the back plate and the diaphragm, and defining a plurality of acoustic holes and an upper insulation layer provided on the substrate, covering the back plate, and holding the back plate to space the back plate from the diaphragm, the upper insulation layer having a flat plate shape to prevent sagging of the back plate.

Abstract: A method for fabricating a vertical transistor device includes forming a first plurality of fins in a first device region and a second plurality of fins in a second device region on a substrate. The first plurality of fins have a SiGe portion exposed above a top surface of the first region and a portion of the second plurality of fins are exposed above a top surface of the second region. The method further includes depositing a first GeO2 layer on the top surface of the device and over the exposed SiGe portion of the first plurality of fins and the exposed portion of the second plurality of fins.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: A thin film transistor, a manufacturing method thereof, an array substrate and a display panel are provided. The thin film transistor includes: a base substrate; and a gate electrode, a gate insulating layer, an active layer and a source/drain electrode layer which are on the base substrate. The source/drain electrode layer includes a source electrode and a drain electrode. The thin film transistor further includes a light blocking layer surrounding the active layer.

Abstract: A semiconductor device includes a semiconductor substrate, a trench provided in the semiconductor substrate, a trench gate formed in the trench, a vertical transistor having the trench gate, an active region having the vertical transistor, a field region surrounding the active region and having a protection diode, and a field insulating film formed on a surface of the semiconductor substrate, the protection diode being formed on the field insulating film. The trench gate includes a first polysilicon layer and has an embedded part embedded in the trench and an extension part connected to the embedded part and extending onto the surface of the semiconductor substrate, the protection diode includes a second polysilicon layer thicker than the first polysilicon layer, and an overlapping part having the second polysilicon layer is formed on the extension part.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: Disclosed is a fan-out antenna packaging method. A front surface of a semiconductor chip is jointed to a top surface of a separating layer; side surfaces and a bottom surface of the semiconductor chip are merged into a packaging layer; the packaging layer is separated from the separating layer to expose the front surface of the semiconductor chip; a rewiring layer is electrically connected to the semiconductor chip; a first antenna structure and a second antenna are stacked on a top surface of the rewiring layer, the antenna structures is electrically connected to the rewiring layer; a through hole runs through the packaging layer and exposes a metal wiring layer in the rewiring layer; and a metal bump electrically connected to the metal wiring layer is formed by using the through hole.