Patents Examined by Raj R Gupta
  • Patent number: 10312175
    Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: June 4, 2019
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Karl D. Hobart, Andrew D. Koehler, Francis J. Kub, Travis J. Anderson, Tatyana I. Feygelson, Marko J. Tadjer, Lunet E. Luna
  • Patent number: 10304921
    Abstract: A display panel may include a detection line overlapped with a non-display region, detection pads connected to the detection line, and an input line connecting an input pad of the detection pads to the detection line. The detection line may include a first portion, which is provided at a level different from a level of the input line and includes an end connected to the input line through a first contact hole in a first contact region, and a second portion, which is provided at a level different from the level of the first portion and is connected to the first portion through a second contact hole in a second contact region. A distance between the first and second portions in a non-contact region may be less than a distance between the first contact hole and the second portion.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: May 28, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonse Lee, Hyunwoong Kim, Joong-Soo Moon, Ae Shin, Ji-eun Lee, Kwangmin Kim, Seungkyu Lee
  • Patent number: 10304892
    Abstract: A solid-state imaging device includes a first substrate, a second substrate, a plurality of first connectors, and a plurality of second connectors. The plurality of first connectors are configured to transmit a first signal. The plurality of second connectors are configured to transmit a second signal. The first signal has at least two levels, and the levels of the first signal discretely vary between the at least two levels. The second signal is a continuous time signal. A first area of a first region is smaller than a second area of a second region. The first region is a projection region of each of the plurality of first connectors in a principal surface of the first substrate. The second region is a projection region of each of the plurality of second connectors in the principal surface.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: May 28, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Jun Aoki
  • Patent number: 10297495
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: May 21, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
  • Patent number: 10298203
    Abstract: A chip stack having a protection structure for semiconductor device package comprises a first chip and a second chip stacked with each other. A first surface of the first chip and a second surface of the second chip are facing to each other. At least one metal pillar is formed on at least one of the first surface and the second surface and connected with the other. At least one protection ring is formed on at least one of the first surface and the second surface and having a first gap with the other. At least one electrical device is formed on at least one of the first surface and the second surface and is located inside at least one of the at least one protection ring, wherein the at least one electrical device includes a temperature sensor.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 21, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Pei-Chun Liao, Po-Wei Ting, Chih-Feng Chiang, Yu-Kai Wu, Yu-Fan Chang, Re-Ching Lin, Shu-Hsiao Tsai, Cheng-Kuo Lin
  • Patent number: 10297689
    Abstract: A transistor includes a vertical channel fin on a bottom source/drain region. The vertical channel fin includes a base portion and an upper portion. The base portion has a width greater than a width of the upper portion and a top surface height greater than a top surface height of the bottom source/drain region. A gate stack formed on sidewalls of the vertical channel fin. Spacers are formed above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed between the spacers.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 21, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10290717
    Abstract: The thin film transistor (TFT) contains a gate electrode metallic layer above a substrate, a gate insulator layer covering the substrate and the gate electrode metallic layer, a first source electrode metallic layer and a first drain electrode metallic layer above the gate insulator layer and separated by a gap, an active layer above the first source and first drain electrode metallic layers filling the gap and forming a ditch in the active layer above the gap, and a second source electrode metallic layer and a second drain electrode metallic layer above the active layer at two lateral sides of the ditch, respectively. The second source/drain electrode metallic layer contacts the first source/drain electrode metallic layer. The TFT has lower parasitic capacitance and takes up less area. As such, when the TFT is applied to a LCD, the reduced space consumed by the TFT enhances pixel's aperture ratio.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: May 14, 2019
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Tuo Feng
  • Patent number: 10290537
    Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: May 14, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mong-sup Lee, Sang-jun Lee, Yoon-ho Son
  • Patent number: 10283612
    Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.
    Type: Grant
    Filed: March 3, 2018
    Date of Patent: May 7, 2019
    Assignee: PIXART IMAGING INCORPORATION
    Inventors: Chih-Ming Sun, Hsin-Hui Hsu, Ming-Han Tsai
  • Patent number: 10283735
    Abstract: An optical assembly in a display device includes a linear polarizer; a first quarter wave plate (QWP) layer under the linear polarizer, the first QWP layer having a negative dispersion characteristic; and a cholesteric liquid crystal (CLC) layer under the linear polarizer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: May 7, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Yeonji Kim, Hyounsung Son, Dongha Yoo, Seongwoo Oh
  • Patent number: 10276821
    Abstract: An electroluminescent (EL) device is disclosed, comprising a high-index layer, having a first refractive index more than 1.8; a first electrode, which is transparent and disposed adjacent to the high-index layer; one or more functional layers, disposed adjacent to the first electrode and opposite to the high-index layer, including a light emitting layer; and, a second electrode, disposed adjacent to the one or more functional layers and opposite to the first electrode; wherein the first electrode has a second refractive index less than 1.7.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: April 30, 2019
    Assignee: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chung-Chih Wu, Min Jiao, Chun-Yang Lu, Wei-Kai Lee
  • Patent number: 10269804
    Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 10260871
    Abstract: A system and method for efficiently determining trajectory and/or location of a device (or user thereof). In a non-limiting example, rotation matrix coefficients may be analyzed in conjunction with stepping information to determine device trajectory and/or location. The system and method may, for example, be implemented in a MEMS sensor system, for example comprising a MEMS gyroscope, MEMS accelerometer, MEMS compass and/or MEMS pressure sensor.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: April 16, 2019
    Assignee: InvenSense, Inc.
    Inventors: Hemabh Shekhar, Shang Hung Lin
  • Patent number: 10261500
    Abstract: A numerical controller calculates a tool path and a tool feed rate based on a cutting point path and a cutting point feed rate instructed by a skiving instruction when a block read from a machining program is the skiving instruction and controls a machining tool based on the calculated tool path and the tool feed rate.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: April 16, 2019
    Assignee: FANUC Corporation
    Inventors: Shuji Ogawa, Motohiko Ito, Yukihiro Hiraishi
  • Patent number: 10236380
    Abstract: Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Patent number: 10209303
    Abstract: A signal processing apparatus includes a recording unit, an operation unit, a processing unit and an abnormality detector. The recording unit records configuration data therein. The operation unit performs arithmetic and logical operations on an input signal and outputs an operation signal indicative of the result of the operations. The operation unit has a circuit configuration defined by the configuration data recorded in the recording unit. The processing unit acquires the operation signal outputted from the operation unit, produces an output signal based on the acquired operation signal and outputs the produced output signal. The abnormality detector detects an abnormality of the circuit configuration of the operation unit. Moreover, in the signal processing apparatus, the processing unit is configured to further acquire an abnormality detection result from the abnormality detector after the acquisition of the operation signal and output the output signal depending on the abnormality detection result.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: February 19, 2019
    Assignee: DENSO CORPORATION
    Inventors: Tetsuya Kimata, Akira Nakashima
  • Patent number: 10211334
    Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: February 19, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Naoki Izumi
  • Patent number: 10211396
    Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. The semiconductor device includes a lower electrode and a magnetic tunnel junction structure disposed on the lower electrode. The magnetic tunnel junction structure includes a seed pattern disposed on the lower electrode. The seed pattern includes an amorphous seed layer and an oxidized seed layer disposed on a surface of the amorphous seed layer. The seed pattern may prevent the lattice structure of the lower electrode from adversely affecting the lattice structure of a pinned magnetic layer of the magnetic tunnel junction structure.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Juhyun Kim, Kiwoong Kim, Sechung Oh, Woochang Lim
  • Patent number: 10204878
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wiring to reduce irregularities caused by the wiring and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: February 12, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Patent number: 10204961
    Abstract: The present application discloses a photodetector substrate comprising an array of a plurality of first electrodes; an array of a plurality of second electrodes, and an insulating block. The plurality of first electrodes and the plurality of second electrode are alternately arranged along a first direction, the plurality of first electrodes are disposed spaced apart from the plurality of second electrodes on a same layer; and the insulating block spaces apart at least a pair of adjacent first electrode and second electrode.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Guo