Abstract: Semiconductor devices and manufacturing method of the same are disclosed. A semiconductor device includes a substrate, a p-type MOS transistor, an n-type MOS transistor and a cured flowable oxide layer. The substrate includes a first region and a second region. The p-type MOS transistor is in the first region. The n-type MOS transistor is in the second region. The cured flowable oxide layer covers the p-type MOS transistor and the n-type MOS transistor, wherein a first strain of the cured flowable oxide layer applying to the p-type MOS transistor is different from a second strain of the cured flowable oxide layer applying to the n-type MOS transistor, and the difference therebetween is greater than 0.002 Gpa.

Abstract: A method for fabricating a semiconductor structure includes providing a dielectric layer on a semiconductor substrate, forming an opening in the dielectric layer to expose a portion of the surface of the semiconductor substrate, forming a metal layer to fill up the opening, and removing the portion of the metal layer formed above the top surface of the dielectric layer by polishing. A metal oxide layer is formed on the surface of the metal layer after polishing. The method further includes removing the metal oxide layer from the top surface of the metal layer, forming a metal barrier layer on the top surface of the metal layer after the removal of the metal oxide layer to provide a more uniform thickness and a denser texture, and converting the metal barrier layer to a metal cap layer by introducing a silicon-containing gas onto a surface of the metal barrier layer.

Abstract: A baseplate circuit is disclosed. The baseplate comprises an IC region, a plurality of WOA regions, a plurality of GOA regions, and a plurality of switches. Each WOA region comprises a plurality of baseplate conducting wires, each of the baseplate conducting wires is electrically connected with the IC region. Each GOA region comprises a plurality of gate lines, each of the gate lines is electrically connected with one of the baseplate conducting wires. Each of the switches is used to electrically connect one of the gate lines and one of the baseplate conducting wires.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a first gate electrode over a substrate while heated at a temperature higher than or equal to 450° C. and lower than the strain point of the substrate, forming a first oxide semiconductor film over the first insulating film, adding oxygen to the first oxide semiconductor film and then forming a second oxide semiconductor film over the first oxide semiconductor film, and performing heat treatment so that part of oxygen contained in the first oxide semiconductor film is transferred to the second oxide semiconductor film.

Abstract: To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.

Abstract: Provided are an apparatus for and a method of processing a substrate. The substrate processing apparatus includes a substrate processing unit to process a substrate using a processing solution containing a mixture of first and second sources; a source supplying part to supply the first and second sources to the substrate processing unit; at least one analyzer to measure a concentration of the second source in the processing solution or a pH value of the processing solution and adjust a measurement reference value of the second source in the processing solution using a standard solution, in which the first and second sources are mixed to have a predetermined concentration or pH value; and a standard solution supplying part to prepare the standard solution using the first and second sources to be supplied from the source supplying part and to supply the standard solution to the at least one analyzer.

Abstract: Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin with a gap in an area directly above the channel fin that has a width greater than a width of the channel fin. Spacers are formed in the gap. The dielectric fill is etched away. A gate stack is formed on sidewalls of the channel fin directly underneath the spacers.

Abstract: A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: Provided is a semiconductor device having dual channels including a first portion and a second portion sharing a buried gate pillar. The buried gate pillar extends from a first surface of a substrate toward a second surface opposite to the first surface. The first portion includes the buried gate pillar, a first gate dielectric layer at a first sidewall of the buried gate pillar and a first doped region set aside the first gate dielectric layer. A first channel is provided in the substrate between the first gate dielectric layer and the first doped region set. The second portion includes the buried gate pillar, a second gate dielectric layer at a second sidewall of the buried gate pillar and a second doped region set aside the second gate dielectric layer. A second channel is provided in the substrate between the second gate dielectric layer and the second doped region set.

Abstract: The present invention relates to a micromechanical device comprising a multi-layer micromechanical structure including only homogenous silicon material. The device layer comprises at least a rotor and at least two stators. At least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a first surface of the device layer and at least some of the rotor and at least two stators are at least partially recessed to at least two different depths of recession from a second surface of the device layer.

Abstract: The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature. More particularly, the surface of the semiconductor feature comprises indium-based III-V compound semiconductor material.

Abstract: A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.

Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.

Abstract: An array substrate comprises a TFT, a data line, a gate line and a passivation layer covering the TFT, the data line and the gate line. The array substrate further includes a first conductive structure and a second conductive structure connected with the first conductive structure, the first conductive structure is disposed on the passivation layer and above the TFT, and the second conductive structure is disposed on the passivation layer and above the data line and/or gate line. A method for manufacturing the array substrate and a display device having such an array substrate are also provided.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

Abstract: A method of forming a semiconductor device is provided including co-implanting a halo species and carbon in a semiconductor layer with a finite tilt angle with respect to a direction perpendicular to the surface of the semiconductor layer. Furthermore, a semiconductor device is provided including an N-channel transistor comprising a halo region made of a halo species with a dopant profile formed in a semiconductor layer and a carbon species implanted in the semiconductor layer with substantially the same dopant profile as the dopant profile of the halo region.

Abstract: A multiple element emitter package is disclosed for increasing color fidelity and heat dissipation, improving current control, and increasing rigidity of the package assembly. In one embodiment, the package comprises a casing with a cavity extending into the interior of the casing from a first main surface. A lead frame is at least partially encased by the casing, the lead frame comprising a plurality of electrically conductive parts carrying a linear array of LEDs. Electrically conductive parts, separate from the parts carrying the LEDs, have a connection pad, wherein the LEDs are electrically coupled to the connection pad, such as by a wire bond. This arrangement allows for a respective electrical signal to be applied to each of the LEDs. The emitter package may be substantially waterproof, and an array of the emitter packages may be used in an LED display such as an indoor and/or outdoor LED screen.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: an Nth metal layer; a bottom electrode over the Nth metal layer; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; a top electrode over the MTJ; and an (N+1)th metal layer over the top electrode; wherein the seed layer has a thickness greater than about one-third of a thickness of the MTJ. Another semiconductor structure is also disclosed. The semiconductor structure includes: a bottom electrode; a seed layer over the bottom electrode; a magnetic tunneling junction (MTJ) over the seed layer; and a top electrode over the MTJ; wherein from a cross-sectional view, the seed layer and the MTJ together have a substantial trapezoidal or rectangular shape, and a slope turning point of a sidewall of the substantial trapezoidal or rectangular shape is at a sidewall of the seed layer. An associated manufacturing method is also disclosed.