Abstract: A device including a plurality of perforations to a semiconductor channel is provided. The device includes a semiconductor structure forming the semiconductor channel. Additionally, the device includes a source contact, a drain contact, and a gate contact to the semiconductor channel. The plurality of perforations can be located in the semiconductor structure below the gate contact. Furthermore, a perforation in the plurality of perforations can extend into the semiconductor structure beyond a location of the semiconductor channel.

Abstract: An array substrate and a manufacturing method thereof and a display device are provided, and the array substrate comprises: a substrate (1); a thin film transistor, a passivation layer (5) and a transparent electrode (6), sequentially formed on the substrate, wherein a groove (51) is formed in an upper surface of the passivation layer (5), and the transparent electrode (6) is provided in the groove (51).

Abstract: A memory device and a method of fabricating a memory device that includes forming a protrusion over a substrate, an etch stop layer over the protrusion, and a stack of alternating material layers over the etch stop layer. The method further includes etching the stack to the etch stop layer to form a memory opening having a first width dimension proximate to the etch stop layer, etching the etch stop layer to provide a void area between the protrusion and a bottom of the memory opening, where the void area has a second width dimension that is larger than the first width dimension, forming a memory film over a sidewall of the memory opening and within the void area over the top surface of the protrusion, etching the memory film to expose the protrusion, and forming a semiconductor channel in the memory opening that is electrically coupled to the protrusion.

Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region formed over a substrate, a drain region formed in the extended drift region, a channel region formed in the extended drift region, a source region formed in the channel region and a dielectric layer formed over the extended drift region. The LDMOS transistor with a dummy gate further comprises an active gate formed over the channel region and a dummy gate formed over the extended drift region. The dummy gate helps to reduce the gate charge of the LDMOS transistor while maintaining the breakdown voltage of the LDMOS transistor.

Abstract: A sensor includes an organic thin-film transistor (OTFT) that operates under low voltage conditions in an aqueous environment. According to an example embodiment, an OTFT includes an organic channel that electrically connects source and drain electrodes, with a gate electrode separated from the channel by a dielectric layer. The channel, gate and dielectric layer are arranged to facilitate switching of the channel region to pass current between the source and drain electrodes, in response to a low voltage applied to the gate electrode, when the channel is exposed to an aqueous solution. The current that is passed is indicative of characteristics of the aqueous solution, and is used to characterize the same. For various implementations, the low voltage operation of the sensor facilitates such characterization with substantially no ionic conduction through an analyte in the aqueous solution.

Abstract: An array substrate and a manufacturing method thereof and a display device are provided, wherein the array substrate includes: a substrate, and a gate electrode, a gate insulating layer, an active layer, a source electrode, a drain electrode and an insulating protection layer sequentially formed on the substrate, and the substrate is further provided with a pixel electrode and a common electrode, and a first leading wire hole connecting the pixel electrode with the drain electrode and a second leading wire hole connecting the common electrode with a common electrode line, the pixel electrode is provided on the substrate, and the gate electrode is directly provided on a transparent conductive layer which is provided at the same layer with the pixel electrode; the pixel electrode is connected with the drain electrode through a first metal connection layer provided in the first leading wire hole, and the first metal connection layer is provided at the same layer with the gate electrode.

Abstract: A semiconductor device includes a substrate, a nanowire, a first structure, and a second structure. The nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate, where the nanowire includes a layer on a surface of the nanowire, where the layer includes at least one of silicide and carbide, where the layer has a substantially uniform shape.

Abstract: An organic electroluminescent element includes electrodes and organic light-emitting layers that are between the electrodes. The organic light-emitting layers contain at least three colors of luminescent materials. A first luminescent material has a maximum light emission wavelength within a range of 430 nm to 480 nm. A second luminescent material has a maximum light emission wavelength within a range of 510 nm to 610 nm. A third luminescent material has a maximum light emission wavelength within a range of 580 nm to 630 nm. An average value of average color rendering indexes in a wide angle region of 30° to 60° with respect to a front direction of a light emission surface is higher than an average color rendering index in the front direction.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer.

Abstract: Provided are resistive random access memory (ReRAM) cells with embedded resistors and methods of fabricating these cells. An embedded resistor may include a metal silicon nitride of a first metal and may be doped with a second metal, which is different from the first metal. The second metal may have less affinity to form covalent bonds with nitrogen than the first metal. As such, the second metal may be unbound and more mobile in the embedded resistor that the first metal. The second metal may help establishing conductive paths in the embedded resistor in addition to the metal nitride resulting in more a stable resistivity despite changing potential applies to the ReRAM cell. In other words, the embedded resistor having such composition will have more linear I-V performance. The concentration of the second metal in the embedded resistor may be substantially less than the concentration of the first metal.

Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

Abstract: A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer.

Abstract: An organic light emitting display device and manufacturing method thereof are disclosed. One inventive aspect includes a first substrate, a second substrate, a pixel unit, a circuit unit, a sealing member and a radiation unit. The pixel unit is formed on the first substrate and comprises an organic light emitting device and a thin-film transistor (TFT). The radiation unit includes radiation fins formed in the sealing member and a radiation layer contacting first ends of the radiation fins.

Abstract: A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.

Abstract: A microphone unit includes a microphone substrate. A plurality of diaphragm units are disposed on the microphone substrate. Each of the diaphragm units includes a diaphragm. A plurality of partition walls are disposed on the microphone substrate. Each of the partition walls surrounds the diaphragm so as to define a first area. A signal processor is disposed at a second area outside the first area and is configured to process signals output from the diaphragm units.

Abstract: A semiconductor light emitting diode is provided. The semiconductor light emitting diode comprises a metal electrode; an n-type cladding over the metal electrode, the n-type cladding comprising a pillar support part formed of an n-type semiconductor material, and a pillar part having a plurality of pillars formed of an n-type semiconductor material over the pillar support part; an active part conformally formed over the pillar part so as to enclose the pillar part and over the pillar support part between the pillar parts, the active part having a quantum well layer and a barrier layer stacked alternately; a p-type cladding conformally formed of a p-type semiconductor material over the active part; and a transparent electrode formed over the p-type cladding.

Abstract: A light-emitting device includes first and second semiconductor layers and a light-emitting layer between the first and second semiconductor layers. The light-emitting device also includes an improved electrode structures.

Abstract: A semiconductor system may include a first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.