Patents Examined by Raj R Gupta
  • Semiconductor device and method for manufacturing the same
    Patent number: 9559058
    Abstract: A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: January 31, 2017
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masaki Haneda, Michie Sunayama, Noriyoshi Shimizu, Nobuyuki Ohtsuka, Yoshiyuki Nakao, Takahiro Tabira
  • Method for forming metal semiconductor alloys in contact holes and trenches
    Patent number: 9559202
    Abstract: A semiconductor device is provided that includes a gate structure on a channel region of a substrate. A source region and a drain region are present on opposing sides of the channel region. A first metal semiconductor alloy is present on an upper surface of at least one of the source and drain regions. The first metal semiconductor alloy extends to a sidewall of the gate structure. A dielectric layer is present over the gate structure and the first metal semiconductor alloy. An opening is present through the dielectric layer to a portion of the first metal semiconductor alloy that is separated from the gate structure. A second metal semiconductor alloy is present in the opening, is in direct contact with the first metal semiconductor alloy, and has an upper surface that is vertically offset and is located above the upper surface of the first metal semiconductor alloy.
    Type: Grant
    Filed: October 27, 2014
    Date of Patent: January 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Christian Lavoie, Zhengwen Li, Ahmet S. Ozcan, Filippos Papadatos, Chengwen Pei, Jian Yu
  • Structure for integration of an III-V compound semiconductor on SOI
    Patent number: 9548319
    Abstract: A semiconductor-on-insulator (SOI) substrate is provided that includes a silicon or germanium handle substrate that is miscut from 2 degrees to 8 degrees towards the <111> crystallographic direction or the <100> crystallographic direction. The topmost semiconductor layer is removed from a portion of the SOI substrate, and then a trench having a high aspect ratio is formed within the insulator layer of the SOI substrate and along the <111> crystallographic direction or the <100> crystallographic direction. An III-V compound semiconductor pillar, which includes a lower portion that has a first defect density and an upper portion that has a second defect density that is less than the first defect density, is then formed in the trench.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Alexander Reznicek
  • Calibration curve formation method, impurity concentration measurement method, and semiconductor wafer manufacturing method
    Patent number: 9541452
    Abstract: According to an embodiment, a method of forming a calibration curve is provided. The method includes ion-implanting different doses of an impurity into a plurality of first samples, measuring an intensity of photoluminescence deriving from the impurity by a photoluminescence spectroscopy for the first samples and a second sample made of the same semiconductor. Based on the amount of implanted impurity, the intensity of the photoluminescence, and a concentration of the impurity contained in the second sample measured by a method other than the photoluminescence spectroscopy, a calibration curve is formed.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: January 10, 2017
    Assignee: GlobalWafers Japan Co., Ltd.
    Inventors: Satoko Nakagawa, Kazuhiko Kashima
  • Semiconductor device and manufacturing method of same
    Patent number: 9530859
    Abstract: A manufacturing method for a semiconductor device including a drift layer; a body layer contacting a front surface of the drift layer; an emitter layer provided on a portion of a front surface of the body layer and exposed on the front surface of the substrate; a buffer layer contacting a back surface of the drift layer; a collector layer contacting a back surface of the buffer layer and exposed on a back surface of the substrate; and a gate electrode facing, via an insulator, the body layer in an area where the body layer separates the emitter layer from the drift layer, includes preparing a wafer that includes a first layer, and a second layer layered on a back surface of the first layer and having a higher polycrystalline silicon concentration than the first layer, and forming the buffer layer by implanting and diffusing ions in the second layer.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: December 27, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shuhei Oki, Tsuyoshi Nishiwaki
  • Semiconductor system
    Patent number: 9524952
    Abstract: A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: December 20, 2016
    Assignee: SK Hynix Inc.
    Inventor: Young-Jun Yoon
  • Semiconductor device and method for manufacturing thereof
    Patent number: 9515081
    Abstract: A semiconductor device includes bit lines provided in a semiconductor substrate; an ONO film that is provided along the surface of the semiconductor substrate and is made of a tunnel oxide film, a trap layer, and a top oxide film; and an oxide film that is provided on the surface of the semiconductor substrate in the middle between the bit lines and contacts the side face of the ONO film, in which the film thickness of the oxide film is larger than the sum of the thicknesses of the tunnel oxide film and the top oxide film, and smaller than the thickness of the ONO film.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: December 6, 2016
    Assignee: Cypress Semiconductor Corporation
    Inventors: Yukio Hayakawa, Yukihiro Utsuno
  • Semiconductor device and a method of manufacturing the same
    Patent number: 9508630
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surf ace protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Semiconductor device with bipolar junction transistor cells
    Patent number: 9508711
    Abstract: A semiconductor device includes a bipolar junction transistor cell including an emitter region which is at least partly formed between mesas of a semiconductor body. The emitter region extends between a first surface of the semiconductor body and an emitter bottom plane. The transistor cell further includes a collector region and a base region that separates the emitter region and the collector region.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: November 29, 2016
    Assignee: Infineon Technologies AG
    Inventors: Jens Peter Konrath, Hans-Joachim Schulze
  • Method for forming a thin-film layer pattern, display substrate and manufacturing method thereof, and display device
    Patent number: 9502444
    Abstract: A method for forming a thin-film layer pattern, a display substrate and a manufacturing method thereof, and a display device are provided. The method for forming the thin-film layer pattern comprises: forming a first thin-film layer to be patterned on a substrate; forming a first overcoat (OC) layer on a surface of the first thin-film layer; forming a first overcoat layer pattern by beam melting; and removing the first thin-film layer not covered by the first overcoat layer pattern to form a first thin-film layer pattern. The method adopts beam melting process and hence can improve the accuracy and the resolution of the display substrate, improve the product quality and reduce the manufacturing cost.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: November 22, 2016
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Display Technology Co., Ltd.
    Inventors: Liyan Xu, Ming Tian, Junwei Wang
  • Manufacturing method of semiconductor device
    Patent number: 9496411
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first insulating film over a first gate electrode over a substrate while heated at a temperature higher than or equal to 450° C. and lower than the strain point of the substrate, forming a first oxide semiconductor film over the first insulating film, adding oxygen to the first oxide semiconductor film and then forming a second oxide semiconductor film over the first oxide semiconductor film, and performing heat treatment so that part of oxygen contained in the first oxide semiconductor film is transferred to the second oxide semiconductor film.
    Type: Grant
    Filed: May 22, 2015
    Date of Patent: November 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tetsuhiro Tanaka, Masayuki Sakakura, Ryo Tokumaru, Yasumasa Yamane, Yuhei Sato
  • High quality electrical contacts between integrated circuit chips
    Patent number: 9490212
    Abstract: Methods and structures of connecting at least two integrated circuits in a 3D arrangement by a zigzag conductive chain are disclosed. The zigzag conductive chain, acting as a spring or self-adaptive contact structure (SACS) in a wafer bonding process, is designed to reduce bonding interface stress, to increase bonding interface reliability, and to have an adjustable height to close or eliminate undesirable opens or voids between two integrated circuits.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 8, 2016
    Inventor: Huilong Zhu
  • Semiconductor device and a method of manufacturing the same
    Patent number: 9484287
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: November 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Semiconductor device and a method of manufacturing the same
    Patent number: 9484286
    Abstract: A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP.
    Type: Grant
    Filed: November 29, 2015
    Date of Patent: November 1, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Shinya Suzuki
  • Organic light-emitting display apparatus
    Patent number: 9484554
    Abstract: An organic light-emitting display apparatus that has high-resolution and high-brightness includes a substrate comprising a major surface; an insulating layer disposed over the substrate and comprising a first inclined surface which is inclined with respect to the major surface and faces away from the substrate; a reflective first pixel electrode disposed over the first inclined surface and configured to cover a portion of the first inclined surface; a first intermediate layer disposed over the first pixel electrode and comprises a light emission layer; and a reflective opposite electrode disposed over the first intermediate layer.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: November 1, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Minwoo Kim, Manseob Choi, Geebum Kim, Katsumasa Yoshii
  • Semiconductor device
    Patent number: 9478564
    Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: October 25, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masashi Tsubuku, Kosei Noda, Kouhei Toyotaka, Kazunori Watanabe, Hikaru Harada
  • Epi-poly etch stop for out of plane spacer defined electrode
    Patent number: 9469522
    Abstract: In one embodiment, a method of forming an out-of-plane electrode includes forming an oxide layer above an upper surface of a device layer, etching an etch stop perimeter defining trench extending through the oxide layer, forming a first cap layer portion on an upper surface of the oxide layer and within the etch stop perimeter defining trench, etching a first electrode perimeter defining trench extending through the first cap layer portion and stopping at the oxide layer, depositing a first material portion within the first electrode perimeter defining trench, depositing a second cap layer portion above the deposited first material portion, and vapor releasing a portion of the oxide layer with the etch stop portion providing a lateral etch stop.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 18, 2016
    Assignee: Robert Bosch GmbH
    Inventors: Andrew Graham, Gary Yama, Gary O'Brien
  • Adjusted fin width in integrated circuitry
    Patent number: 9472550
    Abstract: A method includes growing a plurality of parallel mandrels on a surface of a semiconductor substrate, each mandrel having at least two laterally opposite sidewalls and a predetermined width. The method further includes forming a first type of spacers on the sidewalls of the mandrels, wherein the first type of spacers between two adjacent mandrels are separated by a gap. The predetermined mandrel width is adjusted to close the gap between the adjacent first type of spacers to form a second type of spacers. The mandrels are removed to form a first type of fins from the first type of spacers, and to form a second type of fins from spacers between two adjacent mandrels. The second type of fins are wider than the first type of fins.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: October 18, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Wang, Chih-Sheng Chang, Yi-Tang Lin
  • Nonvolatile memory device
    Patent number: 9472756
    Abstract: According to one embodiment, a nonvolatile memory device includes a first electrode, a second electrode, a variable resistance layer. The variable resistance layer is provided between the first electrode and the second electrode. The variable resistance layer contains impurity of a nonmetallic element. The impurity is at least one selected from the group consisting of S, Se, Te, F, Cl, Br, and I.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Ishikawa, Yoshifumi Nishi, Shosuke Fujii
  • Super junction semiconductor device
    Patent number: 9472614
    Abstract: There is provided a super junction semiconductor device. The super junction semiconductor device includes a cell area and a junction termination area disposed on a substrate, and a transition area disposed between the cell area and the junction termination area, and the cell area, the junction termination area, and the transition area each include one or more unit cells comprising a N-type pillar region and a P-type pillar region among a plurality of N-type pillar regions and a P-type pillar regions that are alternated between the cell area and the junction termination area.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: October 18, 2016
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Moon Soo Cho, Chang Yong Choi, Soon Tak Kwon, Kwang Yeon Jun, Dae Byung Kim, Hyuk Woo