Abstract: A thin-film transistor array including an insulating substrate, gate lines formed on the insulating substrate, source lines formed on the insulating substrate, and transistors each being formed on the insulating substrate at a position corresponding to a respective intersection of the gate lines and the source lines, and formed in a matrix including pixels in rows and columns, each of the transistors including a gate electrode connected to each of the gate lines, a source electrode connected to each of the source lines, a drain electrode, and a pixel electrode connected to the drain electrode. Each of the source lines is connected to a column of pixels, and each of the gate lines includes a first portion connected to a predetermined number of pixels in a row and a second portion connected to pixels in an adjacent row.

Abstract: The present invention provides an organic optoelectronic device and a method for manufacturing the same, in which laser scanning is used to form the electrical connection between the second electrode layer and the contact electrode layer. The present invention can effectively decrease the frequency of replacement of metal masks, significantly shorten the time required for replacing the metal masks, and reduce the down time due to the replacement of metal masks. In addition, the organic optoelectronic device can have a large active area due to the narrow border of the electrical connection formed by the laser scanning.

Abstract: A lighting apparatus is presented. The lighting apparatus includes a semiconductor light source capable of producing blue light of high power density, the semiconductor light source radiationally coupled to a phosphor of formula I in a monolithic form selected from single crystal and ceramic, Ax (M, Mn)Fy (I) where A is Li, Na, K, Rb, Cs, or a combination thereof, M is Si, Ge, Sn, Ti, Zr, Al, Ga, In, Sc, Hf, Y, La, Nb, Ta, Bi, Gd, or a combination thereof, x is an absolute value of a charge of an [MFy] ion; and y is 5, 6, or 7.

Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.

Abstract: An OLED display device includes a substrate, a first protection layer substrate, conductive lines extending substantially in a first direction, a second protection layer, a first electrode overlapping at least a part of the conductive lines, a pixel defining layer including an opening exposing at least a part of the first electrode, an organic light emission layer, and a second electrode. The opening is divided into a first polygon and a second polygon with respect to an imaginary straight line that passes through the opening at a maximum length in the first direction. A planar area of the first polygon is different from a planar area of the second polygon.

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.

Abstract: An epitaxial substrate for semiconductor elements is provided which suppresses the occurrence of current collapse. The epitaxial substrate for the semiconductor elements includes: a semi-insulating free-standing substrate formed of GaN doped with Zn; a buffer layer adjacent to the free-standing substrate; a channel layer adjacent to the buffer layer; and a barrier layer provided on an opposite side of the buffer layer with the channel layer therebetween, wherein the buffer layer is a diffusion suppressing layer formed of AlpGa1-pN (0.7?p?1) and suppresses diffusion of Zn from the free-standing substrate into the channel layer.

Abstract: A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact.

Abstract: The present invention relates to light-converting materials which comprise semiconductor nanoparticles and an unactivated crystalline material, where the semiconductor nanoparticles are located on the surface of the unactivated crystalline material. The present invention furthermore relates to the use of the light-converting material in a light source. The present invention furthermore relates to a light-converting mixture, to a light source, to a lighting unit which contains the light-converting material according to the invention, and to a process for the production of the light source.

Abstract: An organic EL display device according to an embodiment of the present invention includes: a base material; a plurality of pixels; a lower electrode which each of the plurality of pixels is provided with; an organic insulation layer which sections the plurality of pixels; an organic material layer which is disposed on the lower electrode and the organic insulation layer, and includes a plurality of layers; and an upper electrode on the organic material layer. A level difference part is positioned on an upper surface of the organic insulation layer, a first layer included in the organic material layer is divided at the level difference part, or has a thin part being thinner at the level difference part than at a position at which the first layer faces the lower electrode, and a second layer included in the organic material layer is not divided at the level difference part.

Abstract: A display panel may include a detection line overlapped with a non-display region, detection pads connected to the detection line, and an input line connecting an input pad of the detection pads to the detection line. The detection line may include a first portion, which is provided at a level different from a level of the input line and includes an end connected to the input line through a first contact hole in a first contact region, and a second portion, which is provided at a level different from the level of the first portion and is connected to the first portion through a second contact hole in a second contact region. A distance between the first and second portions in a non-contact region may be less than a distance between the first contact hole and the second portion.

Abstract: A method of forming an array of cross point memory cells comprises using two, and only two, masking steps to collectively pattern within the array spaced lower first lines, spaced upper second lines which cross the first lines, and individual programmable devices between the first lines and the second lines where such cross that have an upwardly open generally U-shape vertical cross-section of programmable material laterally between immediately adjacent of the first lines beneath individual of the upper second lines. Arrays of cross point memory cells independent of method of manufacture are disclosed.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: A light emitting device includes a light emitting element; a sub-mount including a sub-mount substrate with a front surface on which the light emitting element is disposed, and a back surface electrode disposed in a back surface that is on a back side of the front surface of the sub-mount substrate; a main-mount in which the sub-mount is disposed, the main-mount including a front surface metal pattern including a wiring electrode bonded to the back surface electrode via solder. The front surface metal pattern has a slit, in a plan view, at a position away from a disposition region in which the sub-mount is disposed.

Abstract: A method of forming matched PFET/NFET spacers with differential widths for SG and EG structures and a method of forming differential width nitride spacers for SG NFET and SG PFET structures and PFET/NFET EG structures and respective resulting devices are provided. Embodiments include providing PFET SG and EG structures and NFET SG and EG structures; forming a first nitride layer over the substrate; forming an oxide liner; forming a second nitride layer on sidewalls of the PFET and NFET EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the PFET SG and EG structures; forming RSD structures on opposite sides of each of the PFET SG and EG structures; removing horizontal portions of the first nitride layer and the oxide liner over the NFET SG and EG structures; and forming RSD structures on opposite sides of each of the NFET SG and EG structures.

Abstract: Some embodiments of the present disclosure relate to an integrated circuit. The integrated circuit has a first semiconductor die and a second semiconductor die. The first semiconductor die is bonded to the second semiconductor die by one or more bonding structures. A first plurality of support structures are disposed between the first semiconductor die and the second semiconductor die. The first plurality of support structures are spaced apart from the one or more bonding structures. The first plurality of support structures are configured to hold together the first semiconductor die and the second semiconductor die.

Abstract: A flexible display substrate, a manufacturing method thereof and a flexible display device are provided. The flexible display substrate includes a flexible substrate and a cathode layer arranged on the flexible substrate and provided with at least one gap.

Abstract: An organic light-emitting circuit structure having a temperature function includes an organic light-emitting diode which has an anode and a cathode opposite to each other; a driving transistor including a first electrode and a second electrode; the first electrode is a source electrode, the second electrode is a drain electrode; or, the first electrode is the drain electrode, the second electrode is the source electrode; a temperature sensitive resistor, which is electrically connected between the driving transistor and the light-emitting device or between the driving transistor and the voltage source. The temperature sensitive resistor increases a resistance value at sensing a temperature increase or decreases the resistance value at sensing a temperature decrease. As a result a current through the organic light-emitting diode stays compensated and stable, thereby ensuring that the organic light-emitting diode keeps emitting light normally under various temperature conditions.

Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.