Abstract: There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size and/or utilize the side surface of an assembled flexible display.

Abstract: Disclosed is an LED module assembly for a display including a first LED module and a second LED module. The first LED module includes a first unit substrate, a plurality of LED chips mounted on the first unit substrate to form a plurality of pixels, and a first light absorbing layer formed on the first unit substrate. The second LED module includes a second unit substrate, a plurality of LED chips mounted on the second unit substrate to form a plurality of pixels, and a second light absorbing layer formed on the second unit substrate. The first unit substrate and the second unit substrate are laterally connected to each other. Each of the first light absorbing layer and the second light absorbing layer includes a plurality of valleys formed between the plurality of pixels.

Abstract: Values are selected for a plurality of controllable parameters of a chemical mechanical polishing system that includes a carrier head with a plurality of zones to apply independently controllable pressures on a substrate. Data is stored relating variation in removal profile on a front surface of the substrate to variation in the controllable parameters, the data including removal at a plurality of positions on the front surface of the substrate, there being a greater number of positions than chambers. A value is determined for each parameter of the plurality of controllable parameters to minimize a difference between a target removal profile and an expected removal profile calculated from the data relating variation in removal profile on a front surface of the substrate to variation in the parameters. The value for each parameter of the plurality of controllable parameters is stored.

Abstract: The present invention provides a method for manufacturing a TFT substrate and a structure thereof. The method for manufacturing the TFT substrate arranges a connection electrode (83) that connects two dual gate TFTs in a third metal layer to prevent the design rules of a connection electrode and a second metal layer of the prior art techniques from being narrowed due to the connection electrode being collectively present on the second metal layer with signal lines of a data line and a voltage supply line so as to facilitate increase of an aperture ratio and definition of a display panel. The present invention provides a TFT substrate structure, which has a simple structure and possesses a high aperture ratio and high definition.

Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.

Abstract: An LDMOS transistor with a dummy gate comprises an extended drift region over a substrate, a drain region in the extended drift region, a channel region in the extended drift region, a source region in the channel region, a first dielectric layer with a first thickness formed over the extended drift region, a second dielectric layer with a second thickness formed over the extended drift region and the channel region, wherein the first thickness is greater than the second thickness, and wherein the first dielectric layer and the second dielectric layer form two steps, a first gate formed over the first dielectric layer and a second gate formed above the second dielectric layer.

Abstract: A chip stack having a protection structure for semiconductor device package, which comprises a first chip and a second chip stacked with each other, wherein said first chip has a first surface, said second chip has a second surface, said first surface and said second surface are two surfaces facing to each other, wherein at least one metal pillar is formed on at least one of said first surface and said second surface and connected with the other, at least one protection ring is formed on at least one of said first surface and said second surface and having a first gap with the other, and at least one electrical device is formed on at least one of said first surface and said second surface, wherein said at least one electrical device is located inside at least one of said at least one protection ring.

Abstract: A semiconductor device includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.

Abstract: A semiconductor device having a first region and a second region is provided. The first region has a first protruding structure and a second protruding structure. The second region has a third protruding structure and a fourth protruding structure. First, second, third, and fourth epi-layers are formed on the first, second, third, and fourth protruding structures, respectively. The first and second epi-layers are covered with a first photoresist layer while leaving the third and fourth epi-layers exposed. A dielectric layer is formed over the first photoresist layer and over the third and fourth epi-layers. A portion of the dielectric layer is covered with a second photoresist layer. The portion of the dielectric layer is formed over the third and fourth epi-layers. Portions of the dielectric layer not protected by the first and second photoresist layers are etched. The first and second photoresist layers are removed.

Abstract: An organic light emitting diode display is disclosed in which a flow control pattern of an organic protective layer is disposed to implement a thin bezel. In an active area and a bezel area defined on a substrate, the flow control pattern disposed reduces the flow of a protective layer so as to minimize area size of the bezel area.

Abstract: The present disclosure provides a pixel structure, an array substrate and a display apparatus, aiming at achieving good display effects in all viewing directions and improved viewing angles. The pixel structure comprises a plurality of transparent electrodes, which are arranged in columns and each transparent electrode corresponds to a subpixel. Each transparent electrode comprises at least two sub-electrode portions, and each sub-electrode portion is provided with a plurality of slits.

Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

Abstract: A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface.

Abstract: A novel semiconductor device or memory device is provided. Alternatively, a semiconductor device or memory device in which storage capacity per unit area is large is provided. The semiconductor device includes a sense amplifier provided to a semiconductor substrate and a memory cell provided over the sense amplifier. The sense amplifier includes a first transistor. The memory cell includes a capacitor over the semiconductor substrate, a second transistor provided over the capacitor, a conductor, and a groove portion. The capacitor includes a first electrode and a second electrode. The first electrode is formed along the groove portion. The second electrode has a region facing the first electrode in the groove portion. The second transistor includes an oxide semiconductor. One of a source and a drain of the second transistor is electrically connected to the second electrode through the conductor.

Abstract: A device structure and method for improving thermal management in highly scaled, high power electronic and optoelectronic devices such as GaN FET and AlGaN/GaN HEMT devices by implementing diamond air bridges into such devices to remove waste heat. The diamond air bridge can be formed from a polycrystalline diamond material layer which can be grown on the surface of a dielectric material layer, on the surface of a III-nitride material, or on the surface of a diamond polycrystalline nucleation layer, and may be optimized to have a high thermal conductivity at the growth interface with the underlying material.

Abstract: The present invention discloses a manufacturing method for a semiconductor device. The manufacturing method includes: providing a substrate; forming a semiconductor stacked structure on the substrate; forming at least apart of a stacked cap layer on the semiconductor stacked structure, wherein the part of the stacked cap layer includes a nitride layer; removing a part of the nitride layer; forming the rest part of the stacked cap layer; forming a protection layer on the stacked cap layer, and etching the protection layer to form an opening, wherein the nitride layer is not exposed by the opening; and introducing an etchant material into the opening to etch the substrate. The present invention also provides a semiconductor device made by the method.

Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

Abstract: A method of manufacturing a spintronics element from laminated layers. The method includes (a) forming a plurality of laminated layers in manufacturing equipment, (b) forming a wafer in the manufacturing equipment, including applying a protection layer directly on a non-magnetic uppermost layer of the laminated layers so that the protection layer prevents alteration of characteristics of the uppermost layer, and (c) exposing the wafer, outside of the manufacturing equipment, to an atmosphere that includes H2O having a partial pressure in the atmosphere equal to or larger than 10?4 Pa.

Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.

Abstract: A method, user interface control arrangement, and a computer program product for controlling a stationary user interface in an industrial process control system as well as to such a process control system. The user interface control arrangement obtains a first live video stream from a video camera monitoring an industrial process at a first location, obtains a process control view for the first location, overlays the process control view on the first live video stream and displays the first live video stream with the overlaid process control view on a display of the user interface.