Patents Examined by Raj R Gupta
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Patent number: 10910604Abstract: The disclosure discloses an organic light-emitting display panel, a method for adjusting color temperature thereof, and a display device, and the organic light-emitting display panel includes: an underlying substrate, and a plurality of light-emitting elements arranged on the underlying substrate; each of the light-emitting elements includes a first electrode, a first light-emitting layer, a second electrode, a second light-emitting layer, and a third electrode arranged on the underlying substrate in that order in a light exit direction of the organic light-emitting display panel, where a wavelength of emitted light from the first light-emitting layer is greater than a wavelength of emitted light from the second light-emitting layer; and the first electrode, the second electrode, and the third electrode are connected respectively with different voltage signal terminals.Type: GrantFiled: March 5, 2018Date of Patent: February 2, 2021Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.Inventors: Shuang Cheng, Jinghua Niu, Xiangcheng Wang, Yuji Hamada, Angran Zhang, Run Yang
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Patent number: 10910375Abstract: Aspects of the disclosure provide a semiconductor device and a method for forming the semiconductor device. The semiconductor device includes a first transistor formed in a first region of the semiconductor device. The first transistor includes a first channel structure extending between a source terminal and a drain terminal of the first transistor. The first transistor includes a second channel structure that is stacked on the first channel structure in a vertical direction above a substrate of the semiconductor device. Further, the first transistor includes a first gate structure configured to wrap around the first channel structure and the second channel structure with a first metal cap between the first channel structure and the second channel structure. The first metal cap has a different work function from another portion of the first gate structure.Type: GrantFiled: September 28, 2018Date of Patent: February 2, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuo-Cheng Ching, Shi Ning Ju, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 10910394Abstract: A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.Type: GrantFiled: May 22, 2020Date of Patent: February 2, 2021Assignee: Renesas Electronics CorporationInventors: Tsutomu Okazaki, Akira Kato, Kan Yasui, Kyoya Nitta, Digh Hisamoto, Yasushi Ishii, Daisuke Okada, Toshihiro Tanaka, Toshikazu Matsui
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Patent number: 10903315Abstract: A technique relates to a semiconductor device. A bottom sacrificial layer is formed on a substrate. A stack is formed over the bottom sacrificial layer and a dummy gate is formed over the stack. The bottom sacrificial layer is removed from under the stack so as to leave an opening. An isolation layer is formed in the opening, the isolation layer being positioned between the stack and the substrate.Type: GrantFiled: September 28, 2018Date of Patent: January 26, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Nicolas Loubet, Robin Hsin Kuo Chao, Julien Frougier, Ruilong Xie
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Patent number: 10886286Abstract: An embodiment includes a substrate having a surface; a first layer that includes a metal and is on the substrate; a second layer that includes the metal and is on the first layer; a first switching device between the first and second layers; a second switching device between the first and second layers; a capacitor between the first and second layers, the capacitor including ferroelectric materials; a memory cell that includes the first switching device and the capacitor; an interconnect line that couples the first and second switching devices to each other; wherein: (a) the surface is substantially disposed in a first plane, and (b) a second plane is parallel to the first plane, the second plane intersecting the first and second switching devices. Other embodiments are addressed herein.Type: GrantFiled: September 28, 2018Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Ashish Verma Penumatcha, Daniel H. Morris, Uygar E. Avci, Ian A. Young
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Patent number: 10872882Abstract: Disclosed is an LED module assembly for a display including a first LED module and a second LED module. The first LED module includes a first unit substrate, a plurality of LED chips mounted on the first unit substrate to form a plurality of pixels, and a first light absorbing layer formed on the first unit substrate. The second LED module includes a second unit substrate, a plurality of LED chips mounted on the second unit substrate to form a plurality of pixels, and a second light absorbing layer formed on the second unit substrate. The first unit substrate and the second unit substrate are laterally connected to each other. Each of the first light absorbing layer and the second light absorbing layer includes a plurality of valleys formed between the plurality of pixels.Type: GrantFiled: November 5, 2019Date of Patent: December 22, 2020Assignee: LUMENS CO., LTD.Inventors: Chunki Min, Keunoh Kim, Huikyeong Noh, Kyungmin Cho
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Patent number: 10867807Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.Type: GrantFiled: November 2, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
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Patent number: 10861937Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.Type: GrantFiled: December 13, 2018Date of Patent: December 8, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
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Patent number: 10854598Abstract: A semiconductor diode with integrated resistor has a semiconductor body with a front surface, a back surface and a diode structure with an anode electrode and a cathode electrode. A resistance layer arranged on the back surface of the semiconductor body provides the integrated resistor.Type: GrantFiled: February 12, 2015Date of Patent: December 1, 2020Assignee: Infineon Technologies Austria AGInventors: Anton Mauder, Philipp Seng
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Patent number: 10847600Abstract: A display device including a resin layer, and a TFT layer being an upper layer with respect to the resin layer, wherein a bending section is provided on a peripheral edge, includes a terminal wiring line that is connected to a terminal in the TFT layer and passes through the bending section, and the terminal wiring line includes a first wiring line and a second wiring line that are positioned on both sides of the bending section, a third wiring line that passes through the bending section and is electrically connected with each of the first wiring line and the second wiring line, and a fourth wiring line that is formed in a layer different from that of the third wiring line and is electrically connected with each of the first wiring line and the second wiring line.Type: GrantFiled: July 28, 2017Date of Patent: November 24, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Takao Saitoh, Masaki Yamanaka, Yohsuke Kanzaki, Seiji Kaneko, Masahiko Miwa
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Patent number: 10840472Abstract: A display device having light emitting elements that respectively include a first electrode formed on a substrate, a laminated structure formed on the first electrode, and a second electrode formed on the laminated structure. The laminated structure is formed by laminating, in the following order from the first electrode side, at least a first organic layer including a first light emitting layer, a charge generation layer in which a first layer into which a first carrier is injected and a second layer into which a second carrier is injected are laminated, and a second organic layer including a second light emitting layer. In a light emitting element including a defect region, the charge generation layer is in a high electrical resistance state or an insulated state in the defect region, while being in a low electrical resistance state in a region other than the defect region.Type: GrantFiled: July 29, 2016Date of Patent: November 17, 2020Assignee: Sony CorporationInventors: Tatsuya Ichikawa, Taizo Tanaka
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Patent number: 10825838Abstract: The present disclosure provides an array substrate, a manufacturing method thereof and a display. By forming a source pattern layer on the base substrate in the present disclosure, the source pattern layer crossing the gate pattern layer maybe mutually insulated from the gate pattern layer through the insulating buffer layer, thus eliminating the dielectric layer in the prior art which is formed to insulate the source pattern layer and the gate pattern layer, further simplifying the structure of the array substrate, and reducing the process steps and process costs.Type: GrantFiled: October 25, 2018Date of Patent: November 3, 2020Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventor: Chuan Wang
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Patent number: 10823555Abstract: A system and method for efficiently determining trajectory and/or location of a device (or user thereof). In a non-limiting example, rotation matrix coefficients may be analyzed in conjunction with stepping information to determine device trajectory and/or location. The system and method may, for example, be implemented in a MEMS sensor system, for example comprising a MEMS gyroscope, MEMS accelerometer, MEMS compass and/or MEMS pressure sensor.Type: GrantFiled: April 16, 2019Date of Patent: November 3, 2020Assignee: InvenSense, Inc.Inventors: Hemabh Shekhar, Shang Hung Lin
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Patent number: 10818801Abstract: A manufacturing method of a thin-film transistor is provided. The method include: forming a gate pattern layer on a substrate; forming a gate insulating layer covering the gate pattern layer; depositing semi-conductive oxide material on the gate insulating layer to form an active pattern layer on the gate insulating layer; depositing reducing material on the active pattern layer to form a reducing pattern layer; and forming a source pattern layer and a drain pattern layer on the reducing pattern layer. A thin-film transistor is further provided.Type: GrantFiled: April 30, 2018Date of Patent: October 27, 2020Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.Inventor: Qianyi Zhang
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Patent number: 10818875Abstract: The present disclosure provides an organic light-emitting display panel and an organic light-emitting display device for improving the uniformity of the display effects of both sides. The organic light-emitting display panel includes an array substrate having a plurality of pixel units; a plurality of organic light-emitting diodes located in the pixel units of the array substrate. The plurality of organic light-emitting diodes includes a plurality of first organic light-emitting diodes and a plurality of second organic light-emitting diodes, wherein the first organic light-emitting diodes are organic bottom light-emitting diodes and the second organic light-emitting diodes are organic top light-emitting diodes. The area of the pixel unit where the first organic light-emitting diodes are located is larger than area of the pixel unit where the second organic light-emitting diodes are located. The organic light-emitting display panel according to the present disclosure is applied in a display device.Type: GrantFiled: March 6, 2018Date of Patent: October 27, 2020Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.Inventors: Xiangcheng Wang, Jinghua Niu, Ding Li
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Patent number: 10804389Abstract: A MOS transistor includes a substrate, a first region, a second region, a source region, a drain region, an active gate stack, and a dummy gate stack. The substrate has a first conductivity. The first region having the first conductivity is formed in the substrate. The second region having a second conductivity is formed in the substrate and is adjacent to the first region. The source region with the second conductivity is formed in the first region. The drain region with the second conductivity is formed in the second region. The active gate stack is disposed on the first region. The dummy gate stack is disposed on the second region, and the dummy gate stack is electrically coupled to a variable voltage.Type: GrantFiled: February 25, 2016Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ching Wu, Po-Jen Wang
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Patent number: 10804436Abstract: A method of forming a light emitting device includes forming a semiconductor light emitting diode, forming a metal layer stack including a first metal layer and a second metal layer on the light emitting diode, and oxidizing the metal layer stack to form transparent conductive layer including at least one conductive metal oxide.Type: GrantFiled: October 5, 2018Date of Patent: October 13, 2020Assignee: GLO ABInventors: Fariba Danesh, Tsun Lau, Richard P. Schneider, Jr., Michael Jansen, Max Batres
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Patent number: 10790311Abstract: The present disclosure relates to a display substrate. The display substrate includes a substrate, a plurality of thin film transistors (TFTs), and data lines. Each of the TFT includes a gate electrode configured on different layer with the data line. A projection of the gate electrode on a plane partially overlaps with the data lines, wherein the data lines are arranged on the plane. A portion of an orthogonal projection of the gate electrode on the plane is arranged on one side of the data line, wherein the portion is not overlapped by the data lines, and the data lines are arranged on the plane.Type: GrantFiled: October 24, 2018Date of Patent: September 29, 2020Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Sikun Hao
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Patent number: 10763447Abstract: The disclosed technology includes systems, devices, and methods associate with producing an organic semiconductor film having electrical dopant molecules distributed to a controlled depth. In an example implementation, a semiconductor device is provided. The semiconductor device can include a first substrate and an organic semiconductor film disposed on the first substrate. The organic semiconductor film includes a first region characterized by electrical dopant molecules distributed to a controlled depth with respect to a first surface of the organic semiconductor film. The semiconductor device further can include an electrode in contact with at least a portion of the first region of the organic semiconductor film.Type: GrantFiled: June 3, 2016Date of Patent: September 1, 2020Assignee: Georgia Tech Research CorporationInventors: Bernard Kippelen, Naoya Aizawa, Canek Fuentes-Hernandez, Junji Kido, Seth Marder, Felipe A. Larrain, Wen-Fang Chou, Vladimir Kolesov
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Patent number: 10756310Abstract: Provided is a display device including a first light emitting layer having an island shape, a second light emitting layer having an island shape, and a third light emitting layer having an island shape, between a lower electrode layer and an upper electrode layer. The first light emitting layer and the second light emitting layer are adjacent in a column direction, and the third light emitting layer is adjacent to the first light emitting layer and the second light emitting layer in a diagonal direction. The first light emitting layer emits blue light, one of the second light emitting layer and the third light emitting layer emits red light, and the other emits green light. A light emitting region of the first light emitting layer is larger than light emitting regions of the second light emitting layer and the third light emitting layer.Type: GrantFiled: September 29, 2017Date of Patent: August 25, 2020Assignee: SHARP KABUSHIKI KAISHAInventor: Kohzoh Nakamura