Abstract: A method for fabricating an electronic device is provided to include: forming a hard mask pattern over a substrate to expose a gate formation region; forming a gate trench by etching the substrate using the hard mask pattern; forming a gate insulating layer over an inner wall of the gate trench; forming a gate electrode filling a lower portion of the gate trench in which the gate insulating layer is formed; forming an insulating material covering a resultant structure in which the gate electrode is formed; forming a gate protective layer having a top surface lower than a bottom surface of the hard mask pattern; removing the hard mask pattern; recessing the substrate so that a top surface of the substrate is lower than the top surface of the gate protective layer; and forming a conductive pattern filling a space formed by the recessing of the substrate.

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

Abstract: A system is disclosed. The system includes a tool cluster. The tool cluster includes a first deposition tool configured to deposit a first layer on a wafer. The tool cluster additionally includes an interferometer tool configured to obtain one or more measurements of the wafer. The tool cluster additionally includes a second deposition tool configured to deposit a second layer on the wafer. The tool cluster additionally includes a vacuum assembly. One or more correctables configured to adjust at least one of the first deposition tool or the second deposition tool are determined based on the one or more measurements. The one or more measurements are obtained between the deposition of the first layer and the deposition of the second layer without breaking the vacuum generated by the vacuum assembly.

Abstract: Solid-state transducers (“SSTs”) and vertical high voltage SSTs having buried contacts are disclosed herein. An SST die in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the transducer structure, and a second semiconductor material at a second side of the transducer structure. The SST can further include a plurality of first contacts at the first side and electrically coupled to the first semiconductor material, and a plurality of second contacts extending from the first side to the second semiconductor material and electrically coupled to the second semiconductor material. An interconnect can be formed between at least one first contact and one second contact. The interconnects can be covered with a plurality of package materials.

Abstract: A method for fabricating semiconductor device includes providing a substrate having a first device region and a second device region. Floating gate structure is formed in the first device region. Liner layer and nitride layer are sequentially deposited over the first device region and the second device region. The floating gate structure is conformally covered. Etching back process is performed on the nitride layer to reduce thickness of the nitride layer. The first device region is still covered by the nitride layer. A photomask layer is formed over the substrate with an opening region to expose the second device region for cleaning. The photomask layer is removed. A gate oxide layer grows on the substrate in the second device region. Anisotropic etching process is performed to remove the nitride layer, resulting in a nitride spacer on a lower portion of a sidewall of the floating gate structure.

Abstract: A semiconductor structure includes a substrate including a first surface, a second surface opposite to the first surface, a first sidewall substantially orthogonal to the first surface and the second surface; an isolation layer surrounding and contacted with the first sidewall of the substrate; a die disposed over the second surface of the substrate; a first conductive bump disposed at the first surface of the substrate; and a second conductive bump disposed between the substrate and the die.

Abstract: A semiconductor device includes: a drift layer of a first conductivity type, implementing a main semiconductor layer; a base region of a second conductivity type provided on an top surface side of the drift layer; a first main electrode region of the first conductivity type provided in an upper part of the base region, having an impurity concentration higher than the main semiconductor layer; a gate electrode buried in a trench penetrating the first main electrode region and the base region through a gate insulating film; a gate screening semiconductor layer of the second conductivity type, being buried under a bottom of the trench; an intermediate semiconductor layer of the first conductivity type sandwiched between the base region and the gate screening semiconductor layer; and a second main electrode region of the second conductivity type provided on a bottom surface side of the drift layer.

Abstract: A method of manufacturing semiconductor products includes: providing a semiconductor product lead frame including a semiconductor die mounting area and an array of electrically conductive leads, molding semiconductor product package molding material, e.g., laser direct structuring material, and forming on the package molding material molded onto the lead frame electrically-conductive lines extending between the semiconductor die mounting area and the array of electrically-conductive leads.

Abstract: A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.

Abstract: A method of producing an optoelectronic component includes providing a carrier including a top side; creating at the top side of the carrier a region that is recessed with respect to a mounting region of the top side to form a step between the mounting region and the recessed region; arranging at the top side of the carrier a metallization extending over the mounting region and the recessed region; creating a separating track in the metallization, wherein the metallization is completely severed at least in sections in the mounting region and is at least not completely severed in the recessed region; and arranging an optoelectronic semiconductor chip above the mounting region of the top side, wherein the optoelectronic semiconductor chip is aligned at the separating track.

Abstract: Micro LED displays offer brighter screens and wider color gamuts than that achievable using traditional LED or OLED displays. Various embodiments are directed to LED and micro LED structures having substrates comprising a metal and oxygen, such as gallium and oxygen, and methods of forming the same. An integrated circuit (IC) structure can include a substrate comprising a metal and oxygen and a core over the substrate. The core can include a group III semiconductor material and nitrogen, and the core can be doped with n-type or p-type dopants. An active layer comprising indium can be provide on a surface of the core. The indium concentration can be adjusted to tune a peak emission wavelength of the IC structure. The IC structure can include a cladding on a surface of the active layer. The cladding can be doped with dopants of opposite type than those used to dope the core.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: A metal film is deposited on a front surface of a semiconductor wafer of silicon. After the semiconductor wafer is received in a chamber, the pressure in the chamber is reduced to a pressure lower than atmospheric pressure. Thereafter, nitrogen gas is supplied into the chamber to return the pressure in the chamber to ordinary pressure, and the front surface of the semiconductor wafer is irradiated with a flash of light, so that a silicide that is a compound of the metal film and silicon is formed. The oxygen concentration in the chamber is significantly lowered during the formation of the silicide because the pressure in the chamber is reduced once to the pressure lower than atmospheric pressure and then returned to the ordinary pressure. This suppresses the increase in resistance of the silicide resulting from the entry of oxygen in the atmosphere in the chamber into defects near the interface between the metal film and a base material.

Abstract: Disclosed is a full-laser scribing method for a large-area copper indium gallium selenide (CIGS) thin-film solar cell module, including: using a laser I to scribe a molybdenum thin film prepared on soda-lime glass to form a first scribed line (P1); preparing the following film layers in sequence on the molybdenum layer in which P1 has been scribed: a CIGS layer, a cadmium sulfide layer and an intrinsic zinc oxide layer; after finishing preparation of the above film layers, using a laser II for scribing to form a second scribed line (P2), wherein the scribed line P2 is parallel with the scribed line P1; and preparing an aluminum-doped zinc oxide layer on the intrinsic zinc oxide layer in which P2 has been scribed, and using a laser III for scribing to form a third scribed line (P3), wherein the scribed line P3 is parallel with the scribed line P1.

Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

Abstract: An annealing object is prepared in which an absorbing film formed of a metal is formed on a surface of a wafer formed of silicon carbide into which an unactivated dopant is implanted. The dopant is activated by causing a laser beam to be incident into the absorbing film. A power density of the laser beam in a surface of the annealing object is a value with which a silicide reaction is caused to occur between the absorbing film and the wafer and a metal silicide film formed by the silicide reaction is evaporated.

Abstract: Sensor data, and the sensors themselves are calibrated, in near real time. Sensor data from multiple mobile machines is received on a mobile machine and used to calibrate sensor data on the mobile machine.

Abstract: The disclosure relates to integrated circuit (IC) structures with a single diffusion break (SDB) and end isolation regions, and methods of forming the same after forming a metal gate. A structure may include: a plurality of fins positioned on a substrate; a plurality of metal gates each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on and extending transversely across the plurality of fins between a pair of the plurality of metal gates; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins; an end isolation region positioned laterally adjacent to a lateral end of one of the plurality of metal gates; and an insulator cap positioned on an upper surface of at least a portion of one of the plurality of metal gates.

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.