Abstract: A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.

Abstract: A vertical ultraviolet light-emitting diode has, on an aluminum polar plane of an n-type AlN single crystal substrate, a layer represented by n-type AlXGa1-XN (wherein X is a rational number satisfying 0.5?X?1.0), an active layer, a layer represented by p-type AlYGa1-YN (wherein Y is a rational number satisfying 0.5?Y?1.0) and a p-type GaN layer in this order and which is equipped with a p-electrode formed on the p-type GaN layer and an n-electrode partially provided on a plane on the opposite side to the aluminum polar plane of the n-type AlN single crystal substrate, preferably an n-electrode formed by providing at least one opening functioning as a light extraction window, wherein the shortest distance between the n-electrode and an arbitrary point in a portion where the n-electrode is not provided, is not more than 400 ?m.

Abstract: Techniques are presented for ensuring alignment marks are available for use and patterning magnetoresistive devices following the deposition of layers used to form the magnetoresistive devices. In some cases, the plurality of layers corresponding to the magnetoresistive devices are selectively etched in order to expose the underlying alignment marks, whereas in other embodiments, the deposition of the plurality of layers is controlled by deposition tool tabs that prevent the materials from obscuring the underlying alignment marks.

Abstract: In an example, there is disclosed a chemical compound, including a transition metal, a post-transition metal, a metalloid, and a nonmetal. By way of non-limiting example, the post-transition metal may be aluminum. The transition metal is selected from the group consisting of tungsten, tantalum, hafnium, molybdenum, niobium, zirconium, vanadium, and titanium. The metalloid may be boron or silicon. The nonmetal may be carbon or nitrogen. The compound may be used, for example, as a barrier material in an integrated circuit.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: A method for producing a component may include providing a composite including a semiconductor layer stack, a first connection layer and a second connection layer, wherein the first and second connection layers are arranged on the semiconductor layer stack, are assigned to different electrical polarities and are configured for the electrical contacting of the component to be produced, applying a molded body material on the composite for forming a molded body, such that in a plan view of the semiconductor layer stack the molded body covers the first connection layer and the second connection layer, forming a first cutout and a second cutout through the molded body for exposing the connection layers in places, and filling the first and second cutouts with an electrically conductive material for forming through contacts which are electrically conductively connected to the connection layers and extend through the molded body in the vertical direction.

Abstract: Disclosed is a substrate processing apparatus including: a processing chamber that accommodates a substrate; a light source that radiates energy rays for a processing to the substrate in the processing chamber; a rotation driving unit that rotates at least one of the substrate and the light source around an axis intersecting with the substrate in the processing chamber; an opening/closing mechanism that switches between an open state and a closed state; and a controller configured to control the opening/closing mechanism to switch between the open state and the closed state, to increase a light emission amount of the light source in synchronization with the switch of the open state to the closed state by the opening/closing mechanism, and to decrease the light emission amount of the light source in synchronization with the switch of the closed state to the open state by the opening/closing mechanism.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers.

Abstract: A semiconductor device includes a plurality of forward conducting insulated-gate bipolar transistor cells configured to conduct a current in a forward operating mode of the semiconductor device and to block a current in a reverse operating mode of the semiconductor device. The semiconductor device also includes a plurality of reverse conducting insulated-gate bipolar transistor cells configured to conduct a current both in the forward operating mode and in the reverse operating mode. A corresponding method for operating a semiconductor device is also disclosed.

Abstract: Techniques are disclosed for increasing the performance of III-N p-channel devices, such as GaN p-channel transistors. Increased performance is obtained by applying compressive strain to the GaN p-channel. Compressive strain is applied to the GaN p-channel by epitaxially growing a source/drain material on or in the GaN. The source/drain material has a larger lattice constant than does the GaN and puts the p-channel under compressive strain. Numerous III-N material systems can be used.

Abstract: An organic light emitting display device comprises two emission portions between first and second electrodes, wherein at least one among the two emission portions includes two emitting layers, whereby efficiency and a color reproduction ratio may be improved.

Abstract: The present invention relates to a method for the production of layers of solid material, in particular for use as wafers. The method may include the following steps: providing a workpiece for the separation of the layers of solid material with the workpiece optionally having at least one exposed surface, producing and/or providing a carrier unit for receiving at least one layer of solid material having the carrier unit optionally having a receiving layer for holding the layer of solid material, attaching the receiving layer to the exposed surface of the workpiece forming a composite structure, producing a break initiation point by means of pre-defined local stress induction in the peripheral region, including at the edge, of the workpiece, and separating the layer of solid material from the workpiece starting from the break initiation point.

Abstract: This application relates to a flexible display screen, comprising: a silicone substrate; a first electrode of polyacrylamide-lithium chloride hydrogel above the silicone substrate; a zinc sulfide-silicone light-emitting layer above the first electrode of polyacrylamide-lithium chloride hydrogel; and a second electrode of polyacrylamide-lithium chloride hydrogel above the zinc sulfide-silicone light-emitting layer.

Abstract: Various embodiments process semiconductor devices. In one embodiment, a release layer is applied to a handler. The at least one singulated semiconductor device is bonded to the handler. The at least one singulated semiconductor device is packaged while it is bonded to the handler. The release layer is ablated by irradiating the release layer through the handler with a laser. The the at least one singulated semiconductor device is removed from the transparent handler after the release layer has been ablated.

Abstract: An electrical device that includes a p-type semiconductor device having a p-type work function gate structure including a first high-k gate dielectric, a first metal containing buffer layer, a first titanium nitride layer having a first thickness present on the metal containing buffer layer, and a first gate conductor contact. A mid gap semiconductor device having a mid gap gate structure including a second high-k gate dielectric, a second metal containing buffer layer, a second titanium nitride layer having a second thickness that is less than the first thickness present, and a second gate conductor contact. An n-type semiconductor device having an n-type work function gate structure including a third high-k gate dielectric present on a channel region of the n-type semiconductor device, a third metal containing buffer layer on the third high-k gate dielectric and a third gate conductor fill present atop the third metal containing buffer layer.

Abstract: The present invention relates to a method and an apparatus for polishing a surface of a substrate having a film whose thickness varies along a circumferential direction of the substrate. The polishing method includes: obtaining a film-thickness distribution in a circumferential direction of a substrate (W); determining a first area having a maximum or minimum film thickness based on the film-thickness distribution; rotating a polishing table (3) holding a polishing pad (2); pressing a surface of the substrate (W) against the polishing pad (2) while rotating the substrate by a polishing head (1); and polishing the first area at a removal rate different from that of a second area in the surface of the substrate (W).

Abstract: Embodiments of this invention relate to a color filter substrate, an array substrate, and a display apparatus. this color filter substrate comprises a substrate; and a color filter layer located on the substrate, wherein the color filter layer comprises a transmissive grating, the transmissive grating comprises a medium array located on the substrate; and a metal layer located on the top surface and the side wall of the medium array, and may comprise a first grating which transmits red light, a second grating which transmits green light, and a third grating which transmits blue light.

Abstract: A micro light emitting diode includes a die-bonding substrate, an adhesive layer, an undoped III-V group semiconductor layer, an N-type III-V group semiconductor layer, a light emitting layer, and a P-type III-V group semiconductor layer. The adhesive layer is disposed on the die-bonding substrate. The undoped III-V group semiconductor layer is disposed on the adhesive layer, and the adhesive layer is between the die-bonding substrate and the undoped III-V group semiconductor layer. The N-type III-V group semiconductor layer is disposed on the undoped III-V group semiconductor layer. The light emitting layer is disposed on the N-type III-V group semiconductor layer. The P-type III-V group semiconductor layer is disposed on the N-type III-V group semiconductor layer, and the light emitting layer is between the N-type III-V group semiconductor layer and the P-type III-V group semiconductor layer.

Abstract: Provided is a capacitor structure including a substrate, a cup-shaped lower electrode, a top supporting layer, a capacitor dielectric layer, and an upper electrode. The cup-shaped lower electrode is located on the substrate. The top supporting layer surrounds the upper portion of the cup-shaped lower electrode. The top supporting layer includes a high-k material. Surfaces of the cup-shaped lower electrode and the top supporting layer are covered by the capacitor dielectric layer. A surface of the capacitor dielectric layer is covered by the upper electrode.

Abstract: The present disclosure provides a photoelectric detection device and a photoelectric detection apparatus. The photoelectric detection device includes a substrate, a reflective structure provided on the substrate and a photoelectric conversion layer provided on the reflective structure, and has a plurality of pixel regions and a plurality of interval regions each provided between two adjacent pixel regions. The photoelectric conversion layer includes a pixel photoelectric conversion portion in the pixel region; the reflective structure includes a pixel reflective portion in the pixel region and an interval reflective portion in the interval region, and the interval reflective portion is configured to reflect light directed to the interval reflective portion from the pixel photoelectric conversion portion back to the pixel photoelectric conversion portion.