Abstract: Methods and systems for selectively depositing dielectric films on a first surface of a substrate relative to a passivation layer previously deposited on a second surface are provided. The methods can include at least one cyclical deposition process used to deposit material on the first surface while the passivation layer is removed, thereby preventing deposition over the passivation layer.

Abstract: Disclosed is a substrate processing apparatus including: a processing chamber that accommodates a substrate; a light source that radiates energy rays for a processing to the substrate in the processing chamber; a rotation driving unit that rotates at least one of the substrate and the light source around an axis intersecting with the substrate in the processing chamber; an opening/closing mechanism that switches between an open state and a closed state; and a controller configured to control the opening/closing mechanism to switch between the open state and the closed state, to increase a light emission amount of the light source in synchronization with the switch of the open state to the closed state by the opening/closing mechanism, and to decrease the light emission amount of the light source in synchronization with the switch of the closed state to the open state by the opening/closing mechanism.

Abstract: In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

Abstract: Examples of a power module include a resin housing including a main body and at least one projection protruding from the main body, and a lead terminal extending outwardly from the main body, wherein a through-hole is provided so as to penetrate the main body and the projection protruding from the main body.

Abstract: A semiconductor die is bonded using epoxy onto a substrate supported on a heating platform. After preheating the substrate with the heating platform to a temperature of between 25° C. and 60° C., an epoxy dispenser deposits an epoxy dot onto the substrate before the semiconductor die is placed onto the epoxy dot with a pick head to thereby bond the semiconductor die onto the substrate.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first layer over a semiconductor substrate. The first layer is made of a first material. The method also includes forming a second layer over the first layer. The second layer is made of a second material that is different from the first material. The second layer has a first opening exposing a portion of a top surface of the first layer. The method also includes heating the first layer and the second layer with a laser beam, depositing a third layer over the second layer and covering a sidewall of the first opening, and etching the first layer through the first opening to form a second opening in the first layer.

Abstract: A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; forming a cap layer overlying the dielectric stack, wherein the cap layer comprises a multi-layer cap layer including at least a first cap layer overlying the charge-trapping layer, and a second cap layer overlying the first cap layer; patterning the cap layer and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to oxidize the first cap layer to form a blocking oxide overlying the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.

Abstract: The semiconductor device includes a vertical Hall element that is provided in a first region of a semiconductor substrate and has a plurality of first electrodes, and a resistive element that is provided in a second region different from the first region in the semiconductor substrate and has a plurality of second electrodes. The plurality of first electrodes and the plurality of second electrodes are connected so that resistances of current paths are substantially the same in any phase in which the vertical Hall element is driven using a spinning current method.

Abstract: A semiconductor device has a semiconductor substrate including an IGBT region operating as an IGBT provided by an emitter layer, a base layer, a drift layer and a collector layer, and a diode region operating as a diode and provided by an anode layer, the drift layer and a cathode layer. The semiconductor substrate further includes a guard ring of a second conduction type, provided in a surface layer of the drift layer in a peripheral region surrounding a device region where the IGBT region and the diode region are adjacent to each other. The cathode layer and the guard ring are positioned such as to satisfy L/d?1.5, where L is a minimum value of a distance between the cathode layer and the guard ring as projected to a plane parallel to a surface of the semiconductor substrate, and d is a thickness of the semiconductor substrate.

Abstract: A display device includes a display panel and at least one electronic component connected to the display panel. The display panel includes a display area and a non-display area disposed around the display area on a plane. The non-display area has a first bending line and a second bending line intersecting the first bending line. The display panel includes a circuit layer and a display element layer including display elements. The circuit layer is disposed in the display area, disposed on a different layer than pixel circuits, and electrically connects the at least electronic component and the driving circuit.

Abstract: A photoresist film is patterned into an array of island shapes with improved critical dimension uniformity and no phase edges by using two alternating phase shifting masks (AltPSMs) and one post expose bake (PEB). The photoresist layer is exposed with a first AltPSM having a line/space (L/S) pattern where light through alternating clear regions on each side of an opaque line is 180° phase shifted. Thereafter, there is a second exposure with a second AltPSM having a L/S pattern where opaque lines are aligned orthogonal to the lengthwise dimension of opaque lines in the first exposure, and with alternating 0° and 180° clear regions. Then, a PEB and subsequent development process are used to form an array of island shapes. The double exposure method enables smaller island shapes than conventional photolithography and uses relatively simple AltPSM designs that are easier to implement in production than other optical enhancement techniques.

Abstract: A fan-out semiconductor package module that is easily manufactured includes a first connection member including a wiring layer, a first passive component mounted on the first connection member, a first encapsulation portion encapsulating at least a portion of the first connection member and the first passive component, a semiconductor chip having an active surface with a connection pad disposed thereon and an inactive surface opposing the active surface and disposed in a first through-hole penetrating through the first connection member and the first encapsulation portion, a second encapsulation portion covering at least a portion of the semiconductor chip and encapsulating at least a portion of the first encapsulation portion and the first connection member, and a second connection member disposed on the first connection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad and the first passive component.

Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor and a capacitor. One of (a) a channel region of e transistor, or (b) a pair of electrodes of the capacitor, is directly above the other of (a) and (b). Additional embodiments and aspects are disclosed.

Abstract: A method of splitting a semiconductor wafer includes: inducing a first stress distribution in the semiconductor wafer by exposing the semiconductor wafer to a first radiation process; inducing a second stress distribution in the semiconductor wafer by exposing the semiconductor wafer to a second radiation process, the second radiation process including applying laser energy to an edge of the semiconductor wafer; and splitting the semiconductor wafer after inducing the first stress distribution and the second stress distribution.

Abstract: An organic light emitting display device comprises two emission portions between first and second electrodes, wherein at least one among the two emission portions includes two emitting layers, whereby efficiency and a color reproduction ratio may be improved.

Abstract: An electroluminescent device, a method of manufacturing the same, and a display device including the same. The electroluminescent device includes a first electrode, a hole transport layer disposed on the first electrode, an emission layer disposed on the hole transport layer and including light emitting particles, an electron transport layer disposed on the emission layer and including nanoparticles having electron transport capability, and a second electrode disposed on the electron transport layer, wherein at least a portion of the nanoparticles having electron transport capability include an inorganic oxide core represented by Chemical Formula 1, an organic ligand attached to a surface of the inorganic oxide core, and a metal-organic compound chemically bound to the surface of the inorganic oxide core.

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber and introducing a plasma-forming gas into the PVD chamber. The plasma-forming gas is an oxygen-containing gas. The method also includes applying a radio frequency (RF) power by a power source to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. The metal target is directly electrically coupled to the power source. The method further includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

Abstract: A micro light-emitting diode display including a substrate and at least one pixel and a reflective layer is provided. The substrate has at least a portion that is transparent to visible light. The pixel includes an opaque electrode, a micro light-emitting diode, and a filling material. The opaque electrode is present on the substrate. The micro light-emitting diode is present on and in contact with the opaque electrode. A vertical projection of the micro light-emitting diode projected on the substrate at least partially overlaps with a vertical projection of the opaque electrode projected on the substrate. The filling material is present on the micro light-emitting diode and the substrate. The reflective layer is present on the filling material. A vertical projection of the reflective layer projected on the substrate at least partially overlaps with said portion of the substrate.

Abstract: A TFT array substrate includes gate electrodes constructed from a first metal film, a first insulating film on the first metal film, channels constructed from a semiconductor film on the first insulating film, source electrodes constructed from a second metal film on the semiconductor film, drain electrodes constructed from the second metal film, pixel electrodes constructed from portions of the semiconductor film having reduced resistances, a second insulating film on the semiconductor film and the second metal film, and a common electrode constructed from a transparent electrode film on the second insulating film. The channels overlap the gate electrodes. The source electrodes and the drain electrodes are connected to first ends and second ends of the channels, respectively. The pixel electrodes are connected to the drain electrodes. The second insulating film includes sections overlapping the pixel electrodes without openings. The common electrode overlaps at least the pixel electrodes.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a free layer (FL) interfaces with a first metal oxide (Mox) layer and second metal oxide (tunnel barrier) to produce perpendicular magnetic anisotropy (PMA) in the FL. In some embodiments, conductive metal channels made of a noble metal are formed in the Mox that is MgO to reduce parasitic resistance. In a second embodiment, a discontinuous MgO layer with a plurality of islands is formed as the Mox layer and a non-magnetic hard mask layer is deposited to fill spaces between adjacent islands and form shorting pathways through the Mox. In another embodiment, end portions between the sides of a center Mox portion and the MTJ sidewall are reduced to form shorting pathways by depositing a reducing metal layer on Mox sidewalls, or performing a reduction process with forming gas, H2, or a reducing species.