Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

Abstract: Surface-aligned lithographic patterning approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, an integrated circuit structure includes a substrate. A plurality of alternating first and second conductive lines is along a first direction of a back end of line (BEOL) metallization layer in a first inter-layer dielectric (ILD) layer above the substrate. A conductive via is on and electrically coupled to one of the conductive lines of the plurality of alternating first and second conductive lines, the conductive via centered over the one of the conductive lines. A second ILD layer is above plurality of alternating first and second conductive lines and laterally adjacent to the conductive via. The second ILD layer has an uppermost surface substantially co-planar with the flat top surface of the conductive via.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A display device and a method of manufacturing the same are provided. A display device includes: a substrate, a semiconductor layer on the substrate, a gate insulating pattern on the semiconductor layer, a plurality of gate electrodes on the gate insulating pattern, and a thin-film transistor spaced apart from the gate insulating pattern, the thin-film transistor including: a source electrode contacting the top surface of the semiconductor layer, a source-drain electrode adjacent to the source electrode, a first of the plurality of gate electrodes being between the source-drain electrode and the source electrode, and a drain electrode adjacent to the source-drain electrode, a second of the plurality of gate electrodes being between the drain electrode and the source-drain electrode.

Abstract: A light-emitting device may comprise a set of layers comprising a substrate layer, and a set of epitaxial layers deposited on the substrate layer. The set of epitaxial layers may include a strained layer. The strained layer may include a set of active zones to be used to generate optical gain. The light-emitting device may comprise a set of trenches etched into a subset of the set of layers of the light-emitting device. The set of trenches may prevent a set of defects or dislocations in a wafer from which the light-emitting device was formed from propagating into the set of active zones.

Abstract: A method of manufacturing a display device including the steps of: forming, on a first mother substrate, pixels including pixel electrodes, gate lines and data lines connected to the pixels; dividing the data lines into groups and connecting the data lines of the same group to one connection line; forming inspection electrodes on the first mother substrate overlapping a shot boundary portion of a mask, the inspection electrodes connected to a plurality of connection lines, respectively; preparing a second mother substrate; forming a common electrode on the second mother substrate; forming a mother panel including the first and second mother substrates and a liquid crystal layer therebetween; applying a first voltage to the common electrode and a second voltage to the inspection electrodes; and determining whether the inspection electrodes and the common electrode are short-circuited based on an image displayed in a display area of the mother panel.

Abstract: A semiconductor structure includes a substrate including a first surface and a second surface opposite to the first surface; a dielectric layer disposed over the second surface or below the first surface; a polymeric layer disposed over or below the dielectric layer; an isolation layer surrounding and contacted with the substrate, the dielectric layer and the polymeric layer; a die disposed over the polymeric layer; a first conductive bump disposed below the first surface of the substrate; and a second conductive bump disposed between the second surface of the substrate and the die.

Abstract: Techniques are disclosed for forming a beaded fin transistor. As will be apparent in light of this disclosure, a transistor including a beaded fin configuration may be formed by starting with a multilayer finned structure, and then selectively etching one or more of the layers to form at least one necked (or relatively narrower) portion, thereby forming a beaded fin structure. The beaded fin transistor configuration has improved gate control over a finned transistor configuration having the same top down area or footprint, because the necked/narrower portions increase gate surface area as compared to a non-necked finned structure, such as finned structures used in finFET devices. Further, because the beaded fin structure remains intact (e.g., as compared to a gate-all-around (GAA) transistor configuration where nanowires are separated from each other), the parasitic capacitance problems caused by GAA transistor configurations are mitigated or eliminated.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: A method of manufacturing a light emitting device comprising: providing an element-structure wafer having a first substrate and a laser element structure on the first substrate, the laser element structure having ridges on a side opposite to the first substrate and raising layers respectively formed above the ridges; bonding a laser element structure side of the element-structure wafer to a second substrate to obtain a bonded wafer; removing at least a portion of the first substrate to obtain a thinned bonded wafer; singulating the thinned bonded wafer to obtain a laser element with the second substrate; mounting the laser element with the second substrate on a heat dissipating member such that a laser element side of the laser element with the second substrate faces the heat dissipating member; and removing the second substrate from the laser element.

Abstract: A variable optical filter is disclosed including a bandpass filter and a blocking filter. The bandpass filter includes a stack of alternating first and second layers, and the blocking filter includes a stack of alternating third and fourth layers. The first, second and fourth materials each comprise different materials, so that a refractive index of the first material is smaller than a refractive index of the second material, which is smaller than a refractive index of the fourth material; while an absorption coefficient of the second material is smaller than an absorption coefficient of the fourth material. The materials can be selected to ensure high index contrast in the blocking filter and low optical losses in the bandpass filter. The first to fourth layers can be deposited directly on a photodetector array.

Abstract: A semiconductor package includes: a connection member having first and second surfaces opposing each other and including a redistribution layer; a support member disposed on the first surface of the connection member, including a cavity, and having an inner sidewall surrounding the cavity of which an upper region is chamfered; a semiconductor chip disposed on the connection member in the cavity and having connection pads electrically connected to the redistribution layer; at least one electronic component disposed between the semiconductor chip and the inner sidewall and having connection terminals electrically connected to the redistribution layer; and an encapsulant encapsulating the semiconductor chip and the at least one electronic component disposed in the cavity.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack; a plurality of first gates disposed on the quantum well stack; a plurality of pairs of spacers, each pair of spacers disposed on opposites sides of an associated first gate, wherein each spacer in a pair has a curved surface that curves away from the associated first gate; and a plurality of second gates disposed on the quantum well stack, wherein the curved surface of each spacer is adjacent to one of the second gates such that at least a portion of each second gate is shaped complementarily to the curved surface of an adjacent spacer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; and one or more gates disposed on the fin. In some such embodiments, the one or more gates may include first, second, and third gates. Spacers may be disposed on the sides of the first and second gates, such that a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate. The third gate may be disposed on the fin between the first and second gates and extend between the first and second spacers.

Abstract: A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.

Abstract: A semiconductor device includes a semiconductor body, first and second electrodes, and a control electrode. The semiconductor body includes first to fourth semiconductor layers. The first electrode is provided on a front surface of the semiconductor body. The second electrode is provided on a back surface of the semiconductor body. The control electrode is provided between the semiconductor body and the first electrode. The second semiconductor layer is positioned between a portion and other portion of the first semiconductor layer in a first direction directed along the front surface. The third semiconductor layer contacts the portion of first semiconductor layer and the second semiconductor layer. The third semiconductor layer includes a first end portion positioned in the portion of the first semiconductor layer and a second end portion positioned in the second semiconductor layer. The fourth semiconductor layer is selectively provided in the second end portion.

Abstract: The present disclosure relates a display device including a semiconductor light emitting device, and a substrate having a receiving groove in which the semiconductor light emitting device is accommodated, wherein the semiconductor light emitting device includes a first conductive semiconductor layer, a second conductive semiconductor layer disposed at an upper portion of the first conductive semiconductor layer, a first conductive electrode disposed on the first conductive semiconductor layer, and a second conductive electrode disposed on the second conductive semiconductor layer, and spaced apart from the first conductive electrode along a horizontal direction, wherein when the semiconductor light emitting device is assembled into the receiving groove, the first conductive semiconductor layer has an asymmetrical shape with respect to at least one direction so that the first conductive electrode and the second conductive electrode are arranged at preset positions.

Abstract: Devices and methods are provided for fabricating vertical field-effect transistor devices for monolithic three-dimensional semiconductor integrated circuit devices. A semiconductor structure is formed to include a substrate and a stack of layers formed on the substrate including a first active semiconductor layer, an insulating layer, and a second active semiconductor layer. A vertical fin structure is formed by patterning the first and second active semiconductor layers and the insulating layer, wherein the vertical fin structure includes first and second vertical semiconductor fins, and an insulating fin spacer disposed between the first and second vertical semiconductor fins. The first and second vertical semiconductor fins are utilized to fabricate first and second vertical field-effect transistor devices on first and second device layers of a monolithic three-dimensional semiconductor integrated circuit device.

Abstract: A manufacturing method for an inkjet printing AMOLED display panel is disclosed. The method includes steps of: manufacturing a TFT backplane, and manufacturing an anode on the TFT backplane; manufacturing a spacer layer for isolating the anode from a pixel definition layer on the anode; manufacturing a pixel definition layer on the TFT backplane, and the pixel definition layer covers the spacer layer; patterning the pixel definition layer to form a notch on the pixel definition layer in order to expose the spacer layer; etching the spacer layer below the notch by an etching solution; and forming an ink layer on the anode by an inkjet printing method. The invention can improve the cleanliness of the anode surface in the AMOLED display panel, reduce the residue, and make the printed light-emitting layer easier to spread evenly, prevent the AMOLED display panel from displaying abnormality.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.