Abstract: A network interface equipment for a bus network employs separate processors and random-access memories for handling bus-protocol and data portions of a data packet. Each processor has access to a separate random-access memory to and from which it moves data. The random-access memories are multiple-ported to permit access by more than one requester with a logic arbitrator to resolve conflicts. A status random-access memory provides communication between the two processors.

Abstract: In a monolithic semi-custom LSI, different types of standard LSI logic sections, each having a predetermined logic configuration and wiring pattern, and each serving as an independent LSI chip; glue circuits such as an SSI and an MSI which have design standards suitable for the same process conditions as those of the standard LSI logic sections, and which constitute a peripheral circuit section of the standard LSI logic sections; a mask pattern section having a wiring region for arbitrarily connecting terminals of the standard LSI logic sections and the peripheral circuit section, and a bonding pad section formed to surround the standard LSI logic sections and the peripheral circuit section to connect them to lead wires, are arranged to minimize the chip size. These constituting elements constitute common hardware as a master. The elements are connected through a single- or multi-layer wiring pattern.

Abstract: A system (10) for transferring data from an image acquisition device (12) to a mainframe computer (14) includes a memory (20) for temporarily storing data received from the image acquisition device (12) prior to transfer to the mainframe computer (14). A direct memory access controller (18) is interconnected between the image acquisition device (12) and the memory (20) for controlling the transfer of blocks of data from the image acquisition device (12) to the memory (20). Structure (30) is provided for controlling the direct memory access controller (18) for partitioning the blocks of data into smaller sized blocks prior to the transfer and storage of this data in the memory (20). Structure (32, 36) functions to transfer the stored blocks of data to the mainframe computer (14).

Abstract: A uniform memory system for use with symbolic computers has a very large virtual address space. No separate files, not directly addressable in the address space of the virtual memory, exist. A special object, the peristent root, defines memory objects which are relatively permanent, such objects being traceable by pointers from the persistent root. A tombstone mechanism is used to prevent objects from referencing deleted objects.

Abstract: A loosely-coupled computer system certains global resources and is made up of stand-alone systems connected by a data link. Each stand-alone system includes a global identifier list which contains identifiers for global resources and the locations of those resources. The global identifier list in each system is identical to those on other systems. Each system further includes a global identifier list maintenance system, an outbound global resource system, an inbound global resource system, and a communications system. When a request for a global resource is made in a stand-alone system, the outbound global resource system determines whether the resource is local or remote. If the resource is remote, the outbound global resource system makes a resource access message and sends it via the communications system to the remote system where the resource is located.

Abstract: A process for uniformly measuring the performance characteristic of a computer peripheral by accommodating for variations in the clock rate of the host computer system is disclosed, where after connecting the target to the host and initializing the system automatically calibrates itself to the clock rate of the host and determines the parameters of the target. The user may then define a select test, a set of test, or a continuous set of tests to be run on the target. In performing the selected test or tests, the system determines the amount of overhead time associated with the host and target, and the data transfer time, before determining the various base access times of the target. Upon the determination of a base access time, the host overhead time is then removed to yield an accurate access time measurement that is independent of variable characteristics of the host computer system.

Abstract: Methods and apparatus for realizing a high performance interface between a processor, constituting part of a reduced instruction set computer (RISC) system, and a set of devices, including memory means. According to the invention, the interface includes three independent buses. A shared processor output bus, a processor input instruction bus, and a bidirectional data bus. The shared processor output address bus coupled the processor and the computer's memory. This bus carries both instructon and data access signals being transmitted by the processor to the memory. The processor input instruction bus also couples the processor and the computer's memory means, but carries instruction signals being transmitted from the memory to the processor. The bidirectional data bus provides a signal path for carrying data signals being transmitted by the memory to the processor and vice-a-versa.

Abstract: A vector processor has a plurality of vector processing units each of which is connected to main storage via a plurality of memory port logic units. Each of the vector processing units has a resource management circuit, thereby managing its resources and the plurality of memory port logic units as resources and reporting information of the memory port logic unit determined to be used to other vector processing units. The plurality of memory port logic units are thus shared by the plurality of vector processing units.

Abstract: A printer support utility provides full support for all compatible printers attached to personal computers operating in a professional office system environment. The utility provides an interface that interprets ANSI printable data and restructures the data to allow for improved printing of underscore, overstrike and highlight, especially in non-impact printers such as laser printers and ink jet printers. The utility reads each line of printable data from an input file and tests the line for a line control indicating a new print line. If not a new print line, the utility scans the line for underscoring, overstriking and highlighting of characters; but if a new print line, the utility converts the scanned line to a personal computer printer line and writes the line to an output file. Finally, the converted print line in the output file is printed.

Abstract: A recovery mechanism restarts jobs following correction of a system failure and automatically marks the jobs for interruption at a logical boundary. The logical boundary is above logical file updating functions such that logical files are in a known state when jobs reach the boundary. When a system failure is detected which has not yet resulted in lost data, an image of working memory, including hardware status is saved on nonvolatile storage. After the failure has been resolved, the system is initially loaded with operating programs (IPL) and working memory is reloaded from the nonvolatile storage. All jobs which were reloaded are marked for interrupt at a machine instruction boundary, and processing is started. After all jobs have reached the boundary, or a predetermined time has elapsed, processing is stopped and the system is re-IPLed. There are few system index recoveries to be performed, since most jobs reached a point where logical files were synchronized with corresponding data.

Abstract: A data transmission system includes a host CPU having an output terminal for repeatedly producing a predetermined number of data blocks in a predetermined sequence in a repeated manner. Each data block is defined by a sequence code for identifying each data block and specific data followed by the sequence code. A plurality of slave CPUs are provided. The host CPU is connected to each slave CPU through a bus structure for the mutual data transmission. Each slave CPU receives all the data blocks and selectively extracts only the necessary data for use in each slave CPU and produces data from its output terminal at a given period within one cycle of the predetermined sequence. The given period for one slave CPU differs from that of another slave CPU, thereby transmitting data to the host CPU without any interferences.

Abstract: A data processing system includes a high speed buffer, or cache, memory for temporarily storing recently executed instructions and a slower main memory in which is stored the system's operating program. Rather than sequentially accessing the cache memory to determine if the next instruction is stored therein and then accessing the main memory if the cache memory does not have the next instruction, system operating speed is increased by simultaneously accessing the cache and main memories. By accessing the main memory during its row address strobe (RAS) precharge time while simultaneously accessing the cache memory, the time necessary for the system's processor unit (PU) to read the next instruction from the main memory when not stored in the cache memory is substantially reduced.

Abstract: A digital image processing system has a pipeline bus for transferring addresses and data in parallel among the components of the system, which include an image memory, an address generator and an intensity processor. The pipeline bus includes a pipeline address bus, a pipeline data bus, and a master timing bus. Through the use of handshake signals, the pipeline bus permits a free flow of pipelined data among the components at whatever rate is necessary to complete the particular processing task. Image data is transferred in the form of N.times.N pixel subimage blocks which can be addressed using a single address.

Abstract: A computer binary numbering system which allows for over range values and determines the sign of the numbers from their two most significant bits. The technique has a particular advantage in computer graphics systems.

Abstract: A compile method to be executed in a digital computer includes the step for detecting among statements in source program codes a first statement defining a first variable and including a polynomial of a plurality of other variables to define the first variable and a second statement including the first variable defined by the first statement so as to use the first variable. The method also includes the steps of judging whether or not the detected second statement satisfies a predetermined copy propagation condition and of replacing the first variable included in the second statement, when a result of the judgement indicates the condition to be satisfied by the second statement, with the polynomial and for eliminating the first statement, with the polynomial anbd for eliminating the first statement. Finally, the method includes the step of generating from a source code after the replacing step object program codes corresponding to the source code.

Abstract: A word processor for setting print out format for each line of a document to be printed by a decorative character printer. The word processor can format data by using various format data bits. The decorative character printer uses decorative character font-identifying bits. The word processor has a device for selecting either a format data input mode or a word data input mode. The format data or word data can be input and stored in the word processor. It will then be determined whether the format data includes decorative character-related data at the head or tail of a line of word data. Decorative characters can then be developed if such data is present in a line of word data.

Abstract: A multifunction test apparatus which is capable of performing total communication network measurments and includes a primary processor linked to a number of dependent processors. The primary processor plays a number of different roles in the functioning of the test system, which roles require substantial interaction between the primary processor and dependent processors. In some test configurations, the primary processor becomes a dependent processor. In other configurations, the primary processor is timeplexed and interleaved with the operation of the dependent processors in performing subfunctions for the dependent processors. The architecture also provides for direct communication and resource sharing between the dependent processors. In another aspect of the subject invention, the primary processor performs overflow calculations for the dependent processors. Finally, the device is arranged such that all test functions are displayed with consistent screen formats.

Abstract: An alignment system for transferring only system words of a subarray embedded in an array in system memory between system memory and a buffer memory. The alignment system utilizes a parallel bus that transfers W system words per cycle and selects only subarray words for transfer between the system memory and the buffer. Additionally, a sequencer schedules and executes combinations of random and block accesses to mamximize bandwidth.

Abstract: A digital memory system wherein a plurality of frames in the memory, each frame holding a page of data, may be rapidly accessed utilizing static column dynamic random access memories (SCRAMs). The SCRAM devices are configured such that a page of data is located on corresponding rows of a plurality of SCRAM devices, the corresponding rows being referred to as frames. Once a row has been activated into static column mode, successive accesses to the same row may be made very rapidly. In the presently preferred embodiments, a plurality of banks are provided, each bank being capable of holding one page of data in static column mode. In the preferred embodiments, a tag register and comparator are provided which are associated with each bank. The tag register contains a portion of the address which previously caused an access to its corresponding bank. An address is presented to all the tag registers and comparators.

Abstract: In an information processing method and system including a secondary storage, a primary storage for storing data blocks of the secondary storage and a directory containing control information for the data blocks stored in the primary storage, the directory is consulted to determine whether a desired data block is in the primary storage, and if it is, the data block is read from the primary storage. The control information of the directory contains pairs of addresses on the primary storage of the data blocks stored in the primary storage and the addresses on the secondary storage.