Abstract: A check up key and a check up display speed key are provided on the inputting apparatus. When the check up key is inputted, a check up display speed controlling apparatus displays the character line of the already inputted document with a continuous shifting of the character line of the already inputted document. When the check up display speed key is inputted, the check up display speed controlling apparatus changes the check up display speed for the display. During the check up of the already inputted document, the character line of the already inputted document is displayed with a continuous shifting and also the check up display speed for the display is set freely, so that the character line of the already inputted document can be edited easily.

Abstract: A method and arrangement for causing both flows of an interleaved computer program to conditionally branch upon satisfaction by a machine state of the condition. By saving for at least one cycle the machine state which satisfied the condition for branching in the first flow, the second flow can then also branch on this saved machine state or condition. Since both flows branch on the same condition, the flows of the program can be kept together, thereby simplifying programming, even for those machines which have dynamic state conditions that can be branched on.

Abstract: In a communications system (10), data is transferred from a physical interface section (64) and two processors, a receive processor (66) and a transmit processor (68). The data is transferred from the physical interface (64) to the receive processor (66) through a receive fifo (112). Data is transferred from the transmit processor (68) to the physical interface (64) through a transmit fifo (110). To prevent the transmit processor (68) and the receive processor (66) from processing data faster than the physical interface (64), clock disabling circuits (1030 and 1032) are utilized wherein the system clock (1033) to the receive processor (66) will be disabled when both the receive fifo (112) is empty and the current instruction performs a read from the receive fifo (112). The system clock (1050) to the transmit processor (68) will be disabled when both the transmit fifo (110) is full and the current instruction executes a write to the transmit fifo.

Abstract: An arrangement and method for restoring a stack which issues a trap handler address for responding to trap occurrences, and which receives addresses of computer instructions from a pipeline, stores and returns these addresses to the pipeline. The arrangement has locations for receiving, storing and returning the addresses. A linked listing of the order in which the addresses to be returned by the stack is maintained. A restoration silo restores the stack from the linked listing after the trap handler address issuance into a state which is the same as if no trap had occurred.

Abstract: A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache.

Abstract: A port emulator circuit implemented on an Apple II peripheral card which enables MS-DOS programs designed to run on an 8086 microprocessor based IBM type personal computer to perform input/output operations on peripheral devices used by 6502 microprocessor based Apple II computers. As the 8086 requires I/O, a state machine, which forms part of the port emulator, performs the required bus arbitration between the 8086 and the 6502 and informs the 6502 of pending requirements of the 8086. The 6502 determines the type of I/O required, and using Apple II hardware resource, performs the I/O operation. The 6502 also places status information concerning the I/O operation in a portion of RAM on the peripheral card, which RAM location emulate the I/O registers found on IBM personal computers.

Abstract: A Space Management System for a Data Access System of a File Access Processor for servicing requests from a set of Application Support Processors, which can exist in a global network, with each Application Support Processor sharing access to data in files stored by the File access Processor. The File Access Processor manages access to a set of data files and information about files held in file directories, which allow for managing file collections, can relate to each other hierarchically, and may be shared. Each Application Support Processor also maintains therein an internal cache of file information to improve performance by reducing communications required with the File Access Processor for informatin about files. The File Access Processor provides the Application Support Processors with information for updating and maintenance of local caches of directory and file description information through a centralized accumulation and distribution of cache change notifications.

Abstract: A disk control system offloads to the disk controller much of the overhead associated with disk operations and makes the CPU available for other work. A command block that fully specifies a user request for a disk operation is forwarded to the disk memory unit. The command block contains a unique identifier for tracking of user requests. User requests are executed by the disk memory unit in an order that is most efficient for the disk drive system. The status of a user request is communicated to the CPU via an interrupt and a status block containing the unique identifier. The status block indicates status conditions such as command read, completion and DMA channel request. The disk driver contains a work queue for user requests that have not been forwarded to the disk memory unit and a pending queue for user requests that are awaiting completion by the disk memory unit. By manipulation of the work queues and pending queues, the disk controller can be automatically reinitialized when an error occurs.

Abstract: A system for loading a program in a distributed system including a plurality of information processing units interconnected by a transmission system comprises an information processing unit for preparing a program and sending the program to the transmission system, another information processing unit having means for receiving the program from the transmission system and storing the program in a memory in accordance with a content of the program, and means for retrieving a program based on program structural information, which program corresponds to the program structural information, and sending the retrieved program to the transmission system, and other information processing units each having means for sending the program structural information to the transmission system and means for selecting a corresponding program from the transmission system and loading the selected program in the unit.

Abstract: A vector processor includes a memory for storing vector data, a processing circuit, a fetch circuit for sequentially fetching elements of a first vector data to be processed from the memory and supplying them to the processing circuit, a generation circuit for generating tag information to designate the fetched vector elements, and a write circuit responsive to the process result by the processing means for writing the tag information generated for the element having a predetermined process result into the memory as one element of a second vector data.

Abstract: A compiler method is disclosed which defines a data flow for a specific complex function to be executed on a plurality of data processing elements in a distributed processing system, by means of defining a plurality of control blocks which are associated with each task. The control blocks are in relocatable code so that they may be associated with any one of several similar types of data processing elements within the distributed processing network. The control blocks include local operating system control blocks, token control, post and wait control blocks, and processing element task execution control blocks. The use of the distributed processing system compiler method enables the quick and easy implementation of complex functions having interdependent processing tasks in a distributed processing system.

Abstract: A multiprocessor computer system consists of n computer modules. Each computer module includes a processor module and a reducing encoder for forming a data word from a code symbol. The code symbols are broadcast to all computer modules for further processing, so that a correct data word comprising k symbols can be reconstructed by means of a symbol-correcting code, while at the most t code symbols may be disturbed. For the connection of an external apparatus, the latter transmits A original versions to a corresponding number of computer modules. The original versions are broadcast to the computer modules as secondary, tertiary, . . . versions during successive broadcast steps. Subsequently, decision steps are taken in the opposite sense, that is to say during a last step but one in majority decision is taken each time on the basis of a secondary version and the tertiary versions originating from the same original version as the relevant secondary version.

Abstract: A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.

Abstract: A video signal processor includes a stored-program controller which concurrently reads two instruction values from a program memory during each instruction cycle. The next instruction used by the video signal processor is selected from between these two values. If the current instruction indicates a conditional branch operation, the value of one of a plurality of conditions internal to the video signal processor determines which of these two instructions is selected. Otherwise, a value provided by the current instruction itself determines which of the two instructions is selected. This configuration of the stored program controller implements a conditional branch facility in which there is no delay in fetching an instruction for either value of the selected condition.

Abstract: The invention is directed to a method by which data from a first synchronous subsystem is transmitted to a second synchronous subsystem physically spaced from the first subsystem such that the system clock is skewed relative to the two subsystems. Pursuant to the invention, the transmitted data cycle time is multiple of the common system cycle time and a clock signal is forwarded with the data from the first subsystem to the second subsystem. The clock signal forwarded with the data provides an indication to the second subsystem of the instants of time at which received data changes. The data change instants are used to generate a binary signal that inverts its value at each such instant. The binary signal is transmitted through a synchronizer to produce a logic signal in the second subsystem. The logic signal is utilized to transmit the received data into the second subsystem in synchronization with the clock of the second subsystem.

Abstract: An apparatus for controlling peripheral equipment includes a circuit for driving the peripheral equipment, first and second registers for storing conditions under which the peripheral equipment is operated, and a timer for counting a time of operation of the peripheral equipment based on data stored in the second register. The content of the first register is written into the second when all zeros are stored in the latter. When the counted time becomes equal to a predetermined time, a time over signal, indicating that an operation time of a specific piece of peripheral equipment is longer than a normal operation time, is produced so that it is possible for a single common timer to count the operation time of a plurality of peripheral equipment.

Abstract: The method of variably displaying search terms includes continuously displaying the names of categories on a video terminal screen. When the cursor is adjacent a category, one data set or search term is displayed, that search term being one of a plurality of terms in a list associated with the particular category. The user displays another term from the list by actuating a scrolling control key input. To select a desired term and move to the next category, the user actuates a select control key input. Therefore, the display system utilizes only two control inputs to select a plurality of terms for a plurality of categories. One list of terms represents control commands that control, among other things, the output of data from the system. One technique of formulating the list is to obtain the data fields from a particular field, corresponding to the category, from all records in a data base. The retrieved data fields are then used as search terms in this dynamically formed list.

Abstract: A data processing system in which the interface for connecting a host controller to a burst multiplexor channel comprises two sections one to handle the transfer of data and the other to handle the transfer of command and status information. The interface also includes logic to monitor the division of any transfer into bursts and logic to arbitrate for the two sections for any given burst.

Abstract: Method and apparatus for prefetching and buffering instructions between a code store and a processing element's decode logic. The apparatus is a code buffer that consists of a code RAM and its supporting logic that implements rules for bringing instructions into the code RAM from the code store and outputting them to the decode logic. These rules determine when writing to the code RAM is blocked and reading from the code RAM is blocked by using the write and read addresses and loop information stored in the supporting logic. The rules guarantee that the instructions to be executed are not overwritten, instructions being executed have, in fact, been brought into the code RAM, and loops are kept in the code RAM until they have been exited. The code buffer handles two types of branch instructions, inside branches to instructions that are within the code RAM and outside branches to instructions in the code store.

Abstract: Mounting volumes (tape reels or disks) to data processing system is managed for reducing the number of mounting operations. A data accumulation algorithm generates mounting criteria.