Abstract: A semiconductor integrated circuit device which inhibits the output of programmed data of its built-in memory to external terminals but outputs the result of a comparison of the programmed data with an input signal supplied from a first external terminal to a second external terminal.

Abstract: A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.

Abstract: A CPU has N-1 ports for concurrently making memory requests and transferring data using a cache with M partitions. Each partition includes a cache directory partition and a corresponding cache data store partition. Each port has a Partition Look-Aside Table (PLAT). Each PLAT has multiple entries that store the most-recent valid memory requests made by its CPU port. A PLAT entry includes a cache partition identifier, a control field, and a congruence-class address for locating associated data in the identified partition. Simultaneous cache accessing in up to N-1 different partitions may be made by N-1 CPU requests have PLAT local hits. The Nth port services global cache misses. An address switch simultaneously connects the CPU requests to up to N different partitions. A PLAT "local hit" occurs when a CPU request equals PLAT valid entry, enabling immediate accessing of the requested data in the identified partition. A PLAT "miss" generates a "global" request sent to all partitions.

Abstract: The present invention includes an interpreter in which a parser examines a message using grammar and lexical tables to produce a parse table. The parse table is compared to data needed in a semantics table to fire a rule. The firing of a rule causes a function table to be evaluated. The function table includes function calls which can perform user desired functions. Among the functions is a generate function which will take the contents of a table and turn it into a message and route the message to a destination where the destination can be a table, process or device. Plural interpreters can be created where each interpreter includes a workspace containing the above-mentioned tables. Each interpreter can perform a different task such as recognizing the meaning of a message in one language and performing some action such as sending out a message in a different language or updating a database.

Abstract: A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuitry. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at locations $XFFF FFFF.

Abstract: A compound document data stream is verified to determine if a compound document conforms to a specified architecture function set. A table driven compound document verifier identifies each deviation from a specified function set in the compound document. The verifier can test the output of document generation and modification applications to determine if they are in compliance with the architecture and to identify those applications that do not comply and in what aspects they deviate from the architecture and its specified function set.

Abstract: A pattern generator permitting to output patterns at high speed and having an operating function, which is suitable for generating test patterns for memory ICs. Although it was known heretofore to increase the operating speed by operating a plurality of pattern generators, for which patterns were generated from memories, in which patterns were previously stored, in parallel, it was not possible to operate pattern generators having an operating function in parallel. A method, by which the order of execution of operation processing instructions is assigned to each of the pattern generators and operation processing instructions are accumulated and allows patterns to be generated at high speed by means of a pattern generator having an operating function. Specifically, the operating processing instructions are grouped and rearranged such that all the pattern generators execute instructions in parallel.

Abstract: In a block data editing apparatus according to the invention, block data to be stored in a block data storage area is mangaged by a block management table for storing block management data which includes reference position data representing a position on a page where the block data is to be displayed, and pointer data which represents a storage position of the block data in the block data storage area. The block data editing apparatus has a further area for temporarily storing the block data designated to be pasted, and also the reference data and the pointer data which correspond to the designated block data. All the block data can be pasted by a single processing operation, and the apparatus can maintain a specific positional relationship between a block frame and the block data. When pasting is executed, the block management data in which the reference position data and the pointer data are updated, is written in the block management table.

Abstract: Disclosed is a method which speeds up interpretive test program code execution and allows rapid changes to the test code. The tester utilized with the present invention uses the interpretive language TPL (Test Program Language) for device test programs. The present invention uses the first execution of a statement in an interpreted environment to build a table of address value pairs corresponding to the values computed by the statement. It then changes the pseudo code of the statement to use a short assembly language routine to write the values in the table fo their appropriate addresses, using the memory mapped features of the test head hardware. This is done by translating each TPL line into pseudo code as it is loaded. The first time a line of code is executed, it builds a table which contains all the values computed and the addresses to which they are written. The next time the statement is executed, the verb pointer points to the turbo software which is executed rather than the TPL statement.

Abstract: A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.

Abstract: A memory of n.times.n digital data, is adapted to receive the n.times.n data from a matrix block in line order after line and to output the data in column after column order. Such a memory is particularly useful for circuits carrying out digital transformations such as cosinus transformations wherein one must first carry out a line transformation then a column summation.The memory is constituted by a network of n.times.n registers REG(i,j) and of n.times.n multiplexers MUX(i,j); the registers are operated at a period T and the multiplexers at a period n.times.T. The connections between the memory inputs and outputs and the register network are alternatively connected at the period n.times.T in order that in a first phase the data are introduced and "horizontally" shifted inside the network and that in a second phase the data are introduced and "vertically" shifted.

Abstract: Disclosed herein is an improved programmable marking device in two preferred embodiments thereof. In a first embodiment, the device includes a keyboard-display portion into which is mounted a removable portable marking device with the marking device having circuitry therein which is electrically connected with the computer in the keyboard-display portion when the removable portable marking device is inserted into a specially designed receptacle in the keyboard-display portion. In the operation of the first embodiment, the keyboard is used to type the message which is desired to be printed by the marking device and the desired message is displayed on the display and corrected as desired while the marking device is plugged into the receptacle. That which is displayed in the display has also been transmitted electrically to a memory device contained within the removable portable marking device.

Abstract: A runaway detecting system for a CPU which has a resetter circuit started by the ON of a power source ON or the output of the CPU for outputting a reset signal to the system including the CPU, and first and second runaway detecting programs, the first runaway detecting program for incrementally or decrementally counting an error by a periodic timer interrupt and overflowing the timer when the error count coincides with a predetermined value, the second runaway detecting program for processing when a timer of the second runaway detecting program is restarted in a short period and outputting a drive signal of the resetter circuit. Thus, the runaway detecting system can detect the runaway of the CPU in a software to prevent in advance the motor or the circuit from damaging due to the runaway of the CPU.

Abstract: A pipeline controlling system executing a preceding instruction in parallel with calculation of an effective address of a succeeding instruction, comprises a first instruction register for storing and holding the preceding instruction, which is in an execute phase; a second instruction register for storing and holding the succeeding instruction, which is in an effective address phase; a register file for storing and holding information to be used for executing the preceding instruction and for calculating the effective address of a succeeding instruction; an effective address calculating portion for calculating the effective address of the succeeding instruction; a comparator for comparing information for designating in the register file a storing location of information to be used for executing the preceding instruction with information for designating in the register file a storing location of information to be used for calculating the effective address of the succeeding instruction; and a controlling circu

Abstract: An electronic postage meter has an improved memory selection circuit wherein custom memory map decoder circuit with resolution down to a single byte location is used to provide selection enabling signals to insure the selection of an appropriate device only when the addresses appropriate to that device are communicated. In accordance with the invention, at least two nonvolatile memories are provided. Writing to either of these nonvolatile memories is inhibited unless one and only one memory is selected. The circuit also prevents the selection of either of the nonvolatile memories in the event that the write strobe signal to the memories is held active.

Abstract: A unit for providing an interface between analog input signals and a digital data processing system bus includes a plurality of analog input channels, sample-and-hold circuits, and an analog-to-digital converter. An optical isolation circuit couples the output of the analog-to-digital converter to a dual-port RAM. The gain of each analog input channel is programmable, as is the address of each input channel in the RAM. Thus the channels can be read in any desired order, and different input voltage ranges can be programmed for each channel. The RAM can be read by an external data processing system via a digital system bus.

Abstract: In a data processing system using a virtual memory addressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value. This invention minimizes the amount of logic required to back out of a software instruction after execution has begun and is faster than checking if all resources are present before any state change is made during the execution of a software instruction.

Abstract: A method for programming a computer system having a display console for displaying images to control at least one of a virtual instrument and an instrument by the steps of displaying on the screen at least one first function-icon that references at least one first control module for controlling at least one first function; displaying on the screen at least one iteration-icon that references iteration control module for controlling multiple iterations of data flow; displaying on the screen at least one first input variable-icon that references at least one first input variable; displaying on the screen at least one first output variable-icon that references at least one first output variable; and assembling on the screen a first acyclic data flow diagram including the at least one first function-icon and the at least one iteration-icon and the at least one first input variable-icon and the at least one first output variable-icon, such that the diagram displays a first procedure for producing at least one value

Abstract: In a multiprocessor system, a program's execution that is controlled by controlling an extended process that spans a plurality of processors. The extended process comprises an user process on one processor for executing object code of the program and stub processes each on an individual one of said remaining processors for accessing system resources required for execution of the program. Each stub process gives the extended process access to the resources associated with the processor executing the stub process. Further, a stub process is unique to one particular extended process. Each stub process is interconnected to the user process by an individual virtual communication channel. The virtual communication channels are identified in each process by a port table that is unique to an individual process. When the user process accesses a local file, the access is through a user file table, a system file table, and an inode table.

Abstract: The portable electronic apparatus of the invention has a memory for storing externally-supplied data, and a central processing unit (CPU 15) for accessing the memory. The memory is divided into a plurality of areas. Each area has pointer data indicating a final address at which the data is written in that area, and a table that lists start and end addresses of each area. A write instruction to be supplied to the portable electronic apparatus consists of a write function code field, a write area designating field, a data string length field, and a data string. The CPU refers to the table based on the write area designating field of the supplied write instruction, reads an end address of the designated area and pointer data, and subtracts the pointer data from the end address, thereby calculating a memory capacity.