Abstract: A CAD system for determining interconnecting lines for (e.g.) information boxes of a flow chart limits the number of vectors (lines parallel with the vertical and horizontal axes of a display device) used to effect an interconnection. The system follows a number of rules which result in a more aesthetic appearance to the output and reduces the risk of short stepwise changes in interconnections thus simplyfying reading of the display.

Abstract: A method for requesting service by a device coupled to a host computer through a communication medium. The host computer sets a service request bit of the device to a first logical value to allow the device to produce a service request signal if the device requires servicing. The device determines that it requires servicing and the device sets an internal flag bit to a first logical value to indicate that the device requires servicing. The device monitors a command from the host computer to see if the command is addressed to the device. If the command is not addressed to the device and if the service request bit is set to a first logical value, then the device generates a service request signal on the medium after the command by holding the communication medium low for a first period of time.

Abstract: In the present invention, a reprogrammable control circuit is disclosed. The reprogrammable control circuit comprises a single-bit register for serially receiving an input bit signal and providing a control signal. The control signal represents the state of the bit stored in the register. A transmission gate means receives the control signal from the single-bit shift register and an input signal and provides an output signal therefrom. The control signal of the bit shift register is used to control the transmission of the input signal to the output signal. A plurality of reprogrammable control circuit which comprises a plurality of bit shift registers, each having a transmission gate means associated therewith is also disclosed. The reprogrammable control circuit can be used in an improved PLA, improved RAM, improved RCIM, improved ALU, improved counter, improved CAM, PCN to improve the reliability of routing signals and power, and to preserve the states of flip-flops.

Abstract: The subject invention employs a system integrated fault-tree analysis (SIFTAN) which has the unique ability to detect all latent hardware and software design defects that could cause unanticipated critical failure of a complex software controlled electronic system. This new approach modifies and then integrates two existing system analysis techniques-namely, hardware fault-tree analysis (HFTA) and software fault-tree analysis (SFTA). The resultant integrated technique is identified as SIFTAN for system integrated fault-tree analysis. Through its integrated hardware/software scope and its critical failure focus, SIFTAN has unique potential to solve the essential analytical limitation behind the software reliability problem. The system exceeds the scope of all current system analysis techniques by providing a system free from all potential critical specification hardware or software design errors.

Abstract: A communications concentrator and message multiplexer featuring direct access from the communications adapters to main memory via direct memory access means which eliminates the usual scanner or polling facility in a concentrator or multiplexer is described. A control microprocessor manages the allocation of memory, the conversion of message protocols and the servicing of interrupts to a plurality of port interface adapter microprocessors. The interface adapter microprocessors directly set up and control the DMA operation instead of having the DMA operation controlled by the control processor. One of the port adapters serves as a service adapter over a dedicated interface allowing a remote disgnostician access to internal registers in the control processor system, access to a dedicated read only storage for servicing, and logical interface to the main control processor for the purpose of entering instructions and directing functional operations to test each component of the system.

Abstract: The invention pertains to the programming of electrically programmable read-only memories (EPROM, EEPROM) made in the form of integrated circuits. To optimize the data programming process, two stages are planned: the first stage is a conventional but short programming stage, designed to memorize data during a relatively short period of time. In the second stage, is a longer repeat programming stage performed in a way which is internal to the integrated circuit, i.e. the data is read in the memory and re-recorded at the same places without its being necssary to apply this data again to the inputs of the integrated circuits.

Abstract: In a system for buffering data, a buffer memory is provided for buffering data output from a data source to an asynchronous data store. When a storage medium is provided in the data store and its storage capacity is exhausted, the data still contained in the buffer memory might not be recorded on the storage medium. Independently of the physical storage capacity of the buffer memory, the logical storage capacity thereof is dynamically adapted to the storage capacity of the data store which is still available. As long as the available storage capacity of the data store is greater than a maximum physical storage capacity of the buffer memory, the buffer memory remains unmodified. When, however, the storage capacity still available in the data store becomes less than the maximum storage capacity of the buffer memory, its logical storage capacity is reduced so that all data intermediately stored in the buffer memory can still always be stored on the storage medium.

Abstract: An improved virtual memory computer system comprising a main processing unit for executing application and operating system software without virtual memory code and independently of virtual memory operation. A dedicated second processing unit is provided for maintaining a memory map, which translates addresses in the main processing unit address space into physical memory addressess of a primary memory. A network interface allows pages or segments of data from a secondary memory connected to a communications network to be transferred into the primary memory in a manner transparent to the operation of the main processing unit. A direct memory access (DMA) circuit transfer the header portion of a network-transferred page of data into a separate auxiliary addressable memory for storage of network overhead information, while the useful data portions of the page are stored directly in locations in the primary addressable memory.

Abstract: A system for controlling access such as time access by a user to a store of information in an information storage system which uses unique codes associated with corresponding number of information units. The system includes a key storage unit (18) which is specifically formatted and can only be accessed by a special read/write program available to the distributor or manufacturer. The key storage unit (18) has a plurality of keys (16) which act as addresses for time units which control the time of operation the program is to be run using the host system clock (14). In response to a valid key being given to the user and being entered to start the program, the number of timed units for this code is rendered subsequently inaccessible, by for example being set to zero automatically so that it cannot readily be used again for free. The program can then be run continuously until an accumulated predetermined time is reached and at the end of the time, program operation is terminated.

Abstract: A system for interconnecting an intelligent controller to a plurality of terminal devices includes a software module, a microprocessor and a device adapter having a plurality of output ports. The system operates under the control of said software module. When the system is powered up, a status for the output ports is assumed and tested under control of a configuration register. If the test is successful, the terminal port remains in that state; if unsuccessful, the state of the terminal port is reversed. The system permits an exchange of operating modes in the terminal devices associated with one port without adversely affecting operation of the remaining ports in the system.

Abstract: A system for programming a computer wherein a computer program is formed into a plurality of self-contained modules or subroutines. Each module or subroutine includes a communications process, a computational process, a data storage process and a feedback process. Each process has a complete truth table and each process is internally mathematically complete. An embodiment of the invention is in the form of a screen generation compiler.

Abstract: Video control circuitry for controlling the video format presented to the cathode ray tube or screen and capable of providing a combination of character generation and cell generation along with other video types of control. The video controller may comprise a video memory means for controlling writing into and reading therefrom and means defining both a memory address and a memory data. There is a video data bus coupled to the video memory means and a processor address bus. A cathode ray tube controller has address lines and the address lines are connected to multiplexer means for selecting either the controller address lines or the processor lines. Control means are provided for controlling the multiplexer means so that in one state thereof the video memory means is addressed from the cathode ray tube controller means and in the other state the video memory means is addressed from the central processing unit address.

Abstract: A digital data processing apparatus utilizes a common bus structure for transferring information between functional units, including a processing unit, a peripheral control unit, and first and second memory units. Unit-to-unit information transfers are executed on the bus structure by pipelining signals representative of a transfer cycle that occurs during plural timing intervals and includes plural phases, where the phases of one cycle are non-overlapping and occur in sequence in different respective timing intervals of the transfer cycle. A signalling element periodically generates a first signal indicative the necessity to refresh at least one dynamic memory element in the first memory unit. A memory refresh element normally responds to that first signal for executing a memory refresh cycle during at least one timing interval common to first and second pipelined transfer cycles. A signal is generated indicating the onset of the memory refresh cycle.

Abstract: A common data structure for access by several application programs is created from a single primitive data element or attribute data object. The attribute data objects can be extracted from node data and node data descriptors in the application program's databases. The attribute data objects are arranged in an attribute file in accordance with certain rules which impose a hierarchical organization upon the attribute data objects. Nonhierarchical relationships may also be used to represent the node data descriptors. The simplicity of the attribute data objects and their lack of limitations make them well suited for use with a wide variety of application programs' databases.

Abstract: A control adapter module in a bus adapter connecting a high-speed pended bus to a slower speed non-pended bus functions as a node of the non-pended bus. An interconnect bus extends between the control module and a response adapter module functioning as a node on the pended bus. Control signals on the interconnect bus generated by the response module comprise status signals having an indefinite assertion duration, and are deasserted only in response to control signals on the interconnect bus generated by the control module, which have a finite duration. Control signals on the interconnect bus generated by the response module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the clock signal of the non-pended bus. Control signals on the interconnect bus generated by the control module are synchronized by a dual-rank synchronizer controlled by two phases of a multiphase clock signal derived from the pended bus clock signal.

Abstract: In sorting an input file on the basis of parameter values of the objects, monotonically varying chains of the objects are formed first. In an inspection phase these chains are selected from which the selection objects will be found as k firsts of the selection objects in the output file, as well as the following selection object. Next, all the objects which on the basis of the parameter value need not function later than the (k+1).sup.th selection object are incorporated in a sub-file, transported to a direct sorting machine and, if necessary, the chain formation is then repeated.

Abstract: A method for extracting and replacing Control Block information in an operating system. An extract replace table is provided to permit application programmers to locate and in certain instances replace items contained in operating system Control Blocks. The user of the application program need not know the precise location of information contained in operating system Control Blocks. The extract/replace table will, upon formulating a request for either extracting or replacing Control Block items, find the requested items and read or replace them. Revisions of operating system programs may be made without regard to the new location of control items. The system user will locate and replace Control Block items by addressing the updated extract/replace tables.

Abstract: A text processing apparatus or word processing system has an input unit for entering character data, an indentation input unit for entering indentation data, a memory for storing the character data and the indentation data, which is connected to or coupled with both the input unit and the indentation input unit, an indentation modifying unit for modifying the position of the indentation data which is stored in the memory, and a control unit for modifying the data stored in the memory according to the position of the indentation data as modified by the indentation modifying unit. This system provides for the modification of document data in response to a change in the position of indentation, the modification or editing of character data which precedes the position of indentation, and the automatic deletion of spaces, which precede an indent start position, when the indentation is released.

Abstract: A branch cache system for use with a pipelined processor having overlapping parcel prefetch and execution stages. The system includes a plurality of memory sets for storing a plurality of indexed sets of predicted branch addresses, and control circuitry which determines whether there is stored in one of the memory sets a predicted branch address which corresponds to a branch instruction fetched by the prefetch stage. The execution stage is commanded, responsive to detection of a predicted branch address corresponding to that branch instruction, to execute the branch instruction to the predicted branch address. Alternatively, the system includes one or more memory sets for storing predicted branch addresses and corresponding alignment values which represent whether the boundary of a prefetched branch instruction, which is prefetched as one or more parcels, aligns with the fixed boundary of the one or more parcels containing that instruction.

Abstract: A reconfigurable processor array (RPA) for performing high speed operations on data arrays and eliminating I/O bottleneck. The array memory has a working side for storing arrays to be processed during a given array operation, and an I/O side for loading an array to be used during a subsequent operation and downloading an array resulting from a preceding operation.