Abstract: A cache memory includes an address back-up register for storing the physical address of the data where errors are generated for backing up the address register, a data array address back-up register for storing data address of the data where errors are generated for backing up the data array address register, and a request code back-up register for storing a preceding request code at the time of the error generation. When an error is detected by the system controller, data is read from the main memory according to the back-up registers and the control register, EYCY register and PSEDO ACK register, of the system controller.

Abstract: A digital computer system including a large number of parallel processing modules (PPM's). Each PPM includes an arithmetic logic unit (ALU), an instruction decoder, and internal bus switching. The main memory is organized in columns and rows with a separate column for each PPM port. Each PPM preferably includes at least three ports to permit parallel transfer of instructions and data to the PPM's. The ports of the PPM's are also connected to segmented lateral transfer buses which operate in conjunction with the internal bus switching of the PPM's to permit tandem ALU operation.

Abstract: An I/O prescription table (I/O PTBL) is associated with a processing program module that is executed by a conventional sequential execution type processor. Each processing program module fetches the input data according to its associated I/O PTBL and stores the output data in the same table. An execution control program makes reference to the I/O PTBL associated with the processing program module, updates the designated I/O PTBL so as to indicate that the corresponding input data is prepared, and starts the processing program module associated with the I/O PTBL which is furnished with all of the necessary input data.

Abstract: A system has a central processor and multiple addressable terminals connected by a communication cable. The terminal itself contains a list of candidate addresses it can use. The terminal determines which of the candidate addresses are already in use by other terminals, and selects one (or more) for itself that is not in use.

Abstract: A file sharing system, comprising a file access processor and a plurality of application support processors; and the file access processor, in turn, includes a central data access system and a storage system is provided to form directories from data in the database, and to change data in that database. Each support processor includes a local cache to acquire and hold directories formed by the data access system; and for each directory acquired by at least one support processor, the data access system further includes a directory gate and a multitude of directory change blocks holding information describing changes in the database that affect the directory. The directory change blocks established for a given directory are arranged in a first chain anchored to the directory gate established for the directory. For each support processor that has acquired at least one directory, the data access system further includes a directory acquired block for each directory acquired by the support processor.

Abstract: A learning algorithm for the N-dimensional Coulomb network is disclosed which is applicable to multi-layer networks. The central concept is to define a potential energy of a collection of memory sites. Then each memory site is an attractor of other memory sites. With the proper definition of attractive and repulsive potentials between various memory sites, it is possible to minimize the energy of the collection of memories. By this method, internal representations may be "built-up" one layer at a time. Following the method of Bachmann et al. a system is considered in which memories of events have already been recorded in a layer of cells. A method is found for the consolidation of the number of memories required to correctly represent the pattern environment. This method is shown to be applicable to a supervised or unsupervised learning paradigm in which pairs of input and output patterns are presented sequentially to the network.

Abstract: A protocol for transferring instructions between asynchronous processors in a computer system is provided. Each instruction transfer requires the transfer of an opcode and a variable number of operands. The transfer is accomplished via a bus which interconnects the processors. The opcode and operands are assembled in a buffer in the sending processor and then transferred to the receiving processor in reverse order, i.e., operands first and opcode last. The receiving processor does not acknowledge any of the transfers until it receives the opcode which is always sent last. Upon receipt of the opcode, the receiving processor knows the instruction transfer is complete and sends the acknowledge signal immediately thereafter.

Abstract: A computer system in which multiple processes may run concurrently includes a window manager for displaying windows associated with different processes. One of the processes represented by a window may be designated as active. Keystrokes are translated by a keyboard driver to events represented by keycodes. The keycodes are routed to processes with which they are associated by reference to a routing table. Unless otherwise indicated, a keycode is routed to the active process. Where a keycode is associated with and transferred to the window manager, subsequent keycodes are stored in a typeahead buffer. The window manager may modify the routing table. After completion of the window manager operation, all keycodes remaining in the buffer are routed to their associated processes as determined by the modified routing table.

Abstract: A plurality of data processor components are distributed along a plurality of intracommunication bus systems, each intracommunication bus system having an address bus and each being assigned a unique set of addresses, with at least one of the components associated with each of the intracommunication bus systems including an address signal generator for generating address signals over the address bus of the associated intracommunication bus system. An intercommunication bus system is utilized in combination with a plurality of link interface units, with each link interface unit connected between the intercommunication bus system and a corresponding one of the intracommunicaton bus systems, for carrying out communication of information over the intercommunication bus system between first and second of the intracommunication bus systems, in response to the address signals on the address bus of the corresponding one of the intercommunication bus systems. A related method is also provided.

Abstract: An improved data processor architecture is provided having integrated circuit (IC) memories. Provision is made for dynamic memories with a memory refresh arrangement. Memory refresh is provided in response to instruction execution, synchronized with computer control signals to minimize contention or conflicts with computer operations and to share control circuitry.

Abstract: A data reading and modifying device of a computer system has a main storage for storing first data, portions of which are to be modified by various modifying data. The access speed of the main storage is slower than the speed at which the modifying data is accessed. A controller initiates fetches of first data from the main store and selects the modifying data. A register is coupled to the main storage for receiving and storing first data as it is provided from the main storage. Portions of the register are reserved for modifying data which is preferably inserted into the register before receipt of the first data as controlled by the controller. The first data received from the main storage is inserted into remaining portions of the register and insertion of, first data into portions reserved for modifying data is inhibited, such that modified data is available without a write back to the main storage location of the data to be modified.

Abstract: A signal processing system (10) is described which has a processor (12), a random access memory (14) for storage of data, a read-only memory (16) for storage of both coefficients and instructions, and a selective cache memory (18) for storage of instructions that require high performance, and their associated buses. Instructions selected by the program are stored in the selective cache memory during their first call from the read only memory for use later in the program. An address sequencer (50) is described as one form of a control unit for executing the data stored in the selective cache memory. It generates a sequence of addresses repetitively, counts the number of iterations of the sequence of addresses, and informs the controller when a certain number of iterations have been completed. This creates a conditional branch statement in the program of the signal processing system (10).

Abstract: The system and method provides a user interface tool for simultaneously selecting a menu item and a value, from a range of values, for the menu item. The user interface tool is referred to as a valuator menu, since it allows both the selection of a value from a range of values, and the selection of a menu item from a menu list. As a user moves a cursor over a menu of selectable items on a screen display, the item underneath the cursor is highlighted. In addition, as the user moves the cursor within the highlighted menu item, a value relative to the position of the cursor within that menu item is displayed. This valuator value is dynamically updated as the cursor position changes within the menu item. When the user performs an input selection, i.e. through a mouse button or a keyboard interaction, both the selected menu item and the value, relative to the cursor position, are simultaneously returned to the application program running on the data processing system.

Abstract: A word processing apparatus is capable of detecting the entry of a function or operation during keying of the text into memory, which requires an operator intervention such as the changing of the print element or the changing of the format parameters. Upon the detection of that condition, an automatic operation is invoked by the software process to insert into the text string and memory a stop code. This insures that the playout of the stored text will be interrupted to permit the operator to perform the same or related operation at the same relative position in the text.

Abstract: A data base management system extending structure includes a data base management system and an extended data base language pre-compiler for pre-compiling an extended data base language into a data base language with which the data base management system can make an access. The extended data base language is added with a link attribute information to the data base language, where the link attribute information specifies relationships of representation objectives.

Abstract: An automatic transfer switch with microprocessor and a display which includes clusters or combinations of display cells. There may, for example, be sixteen display cells for a 16-word display. The display cells are driven by two serially connected shift registers, the input of the first of which is interconnected with the microprocessor. Sixteen digital words are supplied in sequence to the shift registers. One portion of the digital word is then provided in parallel to each of the display cells simultaneously but another portion of the word is supplied to an encoding device which tells which of the sixteen display cells will display that word. One 16 word message requires sixteen reiterations performed at high speed so that it appears that all sixteen display devices are actuated simultaneously to display one multi-word message.

Abstract: In a data management system of this invention, data elements to be registered are managed by item information records each comprising a name of the data element, an item code corresponding to an item to which the data element belongs, and a serial number. The relation between item information records is managed by a relation information record expressed by a source item ID, an object item ID, an item code associated with a source corresponding to an item, and a relation ID indicating the relation between the source and object items. The relation ID is given by a relation table. When a search instruction is input, the item information record, the relation information record, and the relation table are referred to, thus obtaining item information to be searched. The item formation record and relation information record can be registered as needed.

Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

Abstract: Storage serialization apparatus in a multiprocessor computer system enables multiple processors to concurrently execute instructions which access storage without materially affecting performance by keeping the amount of storage locked to a minimum, i.e., a page. The duration of serialization need be only for one instruction execution time and only instruction operands need be accommodated for serialization. Each storage request is intercepted by an associative register stack where there are two registers for each operand, one of the two being for operand page crossings. After a processor has locked access to an area of storage, execution of the instruction begins and all other processor are locked out but only with respect to that locked area. Other processors can access other storage areas during the instruction cycle. When the execution of the instruction completes, the processor releases the locked area of storage by invalidating the entries in its associative register array.

Abstract: A microinstruction sequencer capable of directing an arithmetic-logic unit to conduct conditional operations is disclosed and generally includes a ROM and a selection circuit. The ROM has a memory of m bits wide and n words long, wherein for an m bit wide word in the ROM which defines a conditional operation, a first plurality of bits of the m bits are allocated to a first set of bits for instructing the arithmetic-logic unit as to the function it is to perform, a second plurality of bits of the m bits are allocated to a second set of bits for instructing the arithmetic-logic unit as to the function it is to perform, and a third plurality of bits of the m bits are allocated to a set of control bits. The selecting circuit selects one set of bits from at least the first and second set of bits, and includes a controller for receiving the control bits and controlling the selection by the selection circuit in response thereto.