Abstract: An interface for use with a microcomputer is provided with memory that in one operating mode is used as a first-in first-out buffer, and in a second operating mode allows the direct data transfer across the interface. The interface also includes a means for selecting the operating mode thereof.

Abstract: Method and apparatus for dynamically providing virtual storage resources to an operating system control program in a computing complex where the control program controls the concurrent execution of multiple virtual machines confer on the control program the capacity to gain access to virtual storage resources through the creation of pseudo-virtual machine control blocks that are available only to the control program.

Abstract: A method of assuring consistency of constants in a multilanguage software system, includes generating a first set of code written in a first language using a plurality of symbolic constants to represent a corresponding plurality of actual constants. A second set of code is written in a second language using the plurality of symbolic constants to represent the corresponding plurality of actual constants. A common header file is generated which contains information which relates the plurality of symbolic constants to the corresponding plurality of actual constants. The header is included within the first and second sets of code. The symbolic constants in the first and second sets of code are replaced with their corresponding actual constants during a preprocessing step. Any constructs which are not a part of the first language are stripped from the second set of code including the header file.

Abstract: A method and apparatus for fast branching of microcode sequences in a microcomputer. A branch controller provides addresses to a microcode memory and receives addresses and a branch control signal back from the memory for the next microcode to be executed. Prior to determining whether a branch instruction is present at the indicated location in the sequence, the branch controller provides a provisional address to the memory for the next sequential microcode in the sequence assuming that no branching is to occur. Then a determination is made whether a branch instruction is present. If so, the provisional address is changed by inverting one or more address bits to reflect the branching address and the changed address is applied within the same cycle to the memory.

Abstract: A graphic display PC/interface system is described which includes three memory units: a source memory which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory for storing display data units in a manner suitable for operation of a display unit; and a window buffer for transferring display data unit from the source memory to the target memory. The system transfers a quantity of display data unit bytes from the source memory to the target memory by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween.

Abstract: A database of interests is maintained in a distributed computing system to register the individual interests of users in centrally stored non-textual media files, such as digital voice, music, scanned-in image, and video files. Uniquely named piece table style persistent data structures are employed to give users controlled access to the underlying non-textual media files by embedded name reference to such piece tables in ordinary messages or text files, so a database of piece tables is also maintained. A garbage collector periodically enumerates the interest database to delete interest entries which have been invalidated. Aged piece tables are deleted from the reference database when there no longer are any recorded interests referring to them, and non-textual media files are deleted to reclaim the storage space allocated to them when there no longer are any piece tables referring to them.

Abstract: A modular compiler is used to compile code for execution by an agent engine and a plurality of application programs. The modular compiler includes a class independent compiler which parses program code which is to be executed by the agent engine. The modular compiler also includes a class dependent parser for each application program. Each class dependent parser parses program code which is to be executed by its respective application program. When an application program is added to the computing system, an associated class dependent parser is added to the modular compiler. When an application program is removed from the computing system, the associated class dependent parser is removed from the modular compiler.

Abstract: A method provides error protection in a multiprocessor central control unit of a switching system wherein a number of central processors (CP, IOC) as well as a central memory (CMY) are connected in parallel to a central bus system (B:CMY0/B:CMY1). The processors include dual highly-synchronous parallel driven processor units (PU) --apart from a possible tolerable positive timing slip--and integral error detection circuits (V), as well as an integral local memory (LMY), in the ROM-area of which test program sections are stored for testing the respective processors (CP, IOC). Upon the detection of an error by at least one of the error detection circuits (V) of a processor (for example CPx), in the respective processor (CPx), at least if the error is not immediately correctable, the error detection circuit (V in CPx) starts isolating the respective processor (CPx) from the bus system (B:CMY).

Abstract: In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result operand and stored in a general purpose destination register. The evaluated conditions are each provided in discrete form, that is, unencoded, rather than in encoded form.

Abstract: A method for programming a computer system having a display console for displaying inages to control at least one of a virtual instrument and an instrument by the steps of displaying on the screen at least one first function-icon that references at least one first control module for controlling at least one first function; displaying on the screen at least one iteration-icon that references iteration control module for controlling multiple iterations of data flow displaying on the screen at least one first input variable-icon that references at least one first input variable; displaying on the screen at least one first output variable-icon that references at least one first output variable; assembling on the screen a panel and assembling on the screen a first acyclic data flow diagram including the at least one first function-icon and the at least one iteration-icon and the at least one first input variable-icon and the at least one first output variable-ion, such that the diagram displays a first procedure f

Abstract: An input/output channel apparatus includes a system bus controller for generating a memory read request and outputting a memory address. Generation of the memory read request is inhibited in response to a request inhibit instruction generated by a request-inhibit generating section. When a memory bank other than one accessed in response to the immediately preceding memory read request is accessed, the request-inhibit instruction is generated. The request-inhibit instruction is canceled when memory interleaved data on the basis of the memory read requests for the same memory bank are input to a buffer in the apparatus.

Abstract: Apparatus and methods for creating a virtual push button comprise a touch sensitive orthogonal data field input device useably connected within a computing system in which a touch action at the device generates a stream of data related to the location within the field of the touch action. The orthogonal data field input device includes circuitry for sensing the onset of a first touch action and for monitoring the continuity thereof; and the computing system including a second condition sensor for sensing the occurrence of a second predetermined condition; and, computing circuitry for generating the virtual push button upon the concurrence of touch action continuation and the occurrence of the second predetermined condition.

Abstract: A system for preserving, generating, and merging different versions of a common module that utilizes a line file storing the text of every line in a version and addressing each line with a unique line identifier. Any desired version may be generated directly without creating intermediate versions. The unique line identifiers facilitate a merge operation that does not duplicate lines.

Abstract: A modular and hierarchical multiple bus computer architecture in which the master bus and slave bus are substantially identical, and communicate through a combination of an interface controller and a shared dual port RAM responsive to a shared RAM controller. Processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. The modularity of the architecture allows the use of standard peripherals and platform processor engines to expand memory or increase functionality without burdening the master bus processor engine. Each slave bus processor engine is fully functional as an independent processor with mastery over its own bus.

Abstract: The memory control subsystem controls and arbitrates access to a memory shared by a plurality of users. A processor with its cache and input/output devices has direct access to the memory through a direct memory access bus.The controls subsystem comprises a processor controller, a DMA controller and a memory controller.A processor request is buffered into the processor controller and is serviced immediately if the memory controller is available. A simultaneous transfer between the devices and buffers in the DMA controller is possible. If the memory controller is busy, the DMA controller causes the DMA transfer to be interrupted, the processor request to be serviced and the DMA transfer to be resumed afterwards.Write requests made by the processor are buffered into processor controller and an acknowledgement signal is sent to the processor which can resume execution without waiting the memory update completion.

Abstract: In a look-ahead control type of microprocessor, each area of a buffer memory temporarily stores a macroinstruction and a separate tag unit memory is provided for each such area, the tag being binary 1 when a macroinstruction is stored and binary 0 when an area becomes vacant. When one area becomes vacant because its macroinstruction is outputted to a decoder, the tag for that area provides a binary 0 to a NAND circuit which then outputs a binary 1 to one input of an AND gate. If the decoded macroinstruction is not an unconditional branch instruction, the decoder sets a flip-flop to provide a binary 1 to the other input of the AND gate so the AND gate will output a binary 1 to a bus access control logic circuit as a fetch demand signal so an external memory will provide a macroinstruction over an external data bus to the vacant buffer memory area.

Abstract: A data processing system with an apparatus for reducing loop processing time including an address reset circuit that resets the program counter and prefetch counter to the loop beginning address when the program executes the instruction at the loop ending address. The need for repeated address calculation for branching to a loop beginning address after each loop execution cycle is eliminated, thereby speeding up the loop processing.

Abstract: In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided.

Abstract: Backup battery switching circuitry for a microcomputer or a microprocessor includes circuitry for selectively coupling a backup battery to a power supply output terminal of the microcomputer or microprocessor for powering an external circuit such as a static RAM. The backup battery voltage is normally coupled to the power supply output terminal in the absence of a primary power source, but may be isolated from the power supply output terminal when a predetermined voltage is applied to a logic input pin and a predetermined sequence of events is executed by the microcomputer or microprocessor.

Abstract: A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.