Abstract: Disclosed systems and methods address escalated vulnerability attributable to system down time. In at least one embodiment, a customer-selectable threshold of detection establishes the number of days a system is allowed to be “down” before forcing a secured update path as described herein. The threshold may represent a compromise and balance between inconvenience and security based on each customer's preference. Tracking of system down time or offline time may be managed via EC/SBIOS and a real time clock (RTC) timer. The system down time may then be compared to the customer setting, e.g., whenever the system is booted.

Abstract: A wireless mouse operatively coupled to an information handling system including a wireless mouse microcontroller and a wireless mouse power management unit (PMU) to provide power to the wireless mouse microcontroller and the wireless mouse PMU operatively coupled to a battery and an ultracapacitor. The wireless mouse further comprising a click haptic solenoid energy harvester device placed under a wireless mouse button with a striking arm to interface with a mouse button plate when the wireless mouse button is pressed down, the striking arm urging a magnet through the wire coil when the wireless mouse button is pressed down to change the ultracapacitor. The wireless mouse microcontroller determines when the wireless mouse is in a standby mode based on input from an actuation/engagement sensor and, with the wireless mouse PMU, switch a power source from a battery to the ultracapacitor when the wireless mouse is in the standby mode.

Abstract: A port is to couple to another die over a die-to-die (D2D) link and includes a die-to-die (D2D) adapter to determine, from a set of registers, a set of capabilities of the D2D adapter to advertise in a negotiation with a link partner D2D adapter, where the D2D adapter is on a die and the link partner D2D adapter is located on a remote link partner die. A first capabilities advertisement message is sent to the link partner D2D adapter to advertise the set of capabilities to the link partner D2D adapter. A second capabilities advertisement message is received from the link partner D2D adapter, wherein the second capabilities advertisement message identifies a set of capabilities of the link partner D2D adapter. A final configuration of a D2D link is determined to couple the die to the link partner die.

Abstract: Autonomous power control is provided on a storage system to enable service level maximum response time controls to be achieved, while also minimizing power consumption, by enabling service level minimum response times to be specified and enforced. A workload/CPU clock speed model is created for the storage system correlating a maximum number of IOPS that the storage system can process for different CPU clock speeds for each workload type. A service level agreement specifies a maximum storage system response time. A storage system minimum response time is also specified, that is used to identify a target CPU clock speed for the workload type being provided by a host. The CPU clock speed is lowered to reduce energy consumption by the storage system toward the target CPU clock speed, and storage system performance is monitored to ensure that the storage system complies with the storage system maximum response time.

Abstract: A storage processing unit (SPU), which may be resident in a server in a storage system, provides a boot volume to the server and provides storage services. The SPU may execute a process including taking three snapshots of the boot volume respectively after writing an operating system image into the boot volume, after writing component images or otherwise customizing contents of the boot volume, and after the server boots from the boot volume. For updates, stability, or recovery of the storage system, the SPU may promote any of the snapshots to be the boot volume before the server reboots.

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

Abstract: A field programmable gate array (FPGA) including a configurable interconnect fabric connecting a plurality of logic blocks, the configurable interconnect fabric and the logic blocks being configured to implement a data masking circuit configured to: receive input data including data values at a plurality of indices of the input data; select between a data value of the data values and an alternative value using a masking multiplexer to generate masked data, the masking multiplexer being controlled by a mask value of a plurality of mask values at indices corresponding to the indices of the input data; and output the masked data. In some examples, the configurable interconnect fabric and the logic blocks are further configured to implement a mask generation circuit configured to generate the mask values. In some examples, the mask values are received from external memory.

Abstract: A clock recovery circuit includes a reference clock generation unit that generates a reference clock subjected to SSC modulation, a clock recovery unit that recovers an SSC modulated clock of a data signal subjected to the SSC modulation in synchronization with the reference clock, and a modulation signal generation unit that generates a modulation signal based on cycle information indicating a cycle of a FM demodulated signal obtained by performing FM demodulation on the SSC modulated clock recovered by the clock recovery unit and slope information indicating a slope of the FM demodulated signal, in which the reference clock generation unit generates the reference clock by performing the SSC modulation on a clock of a VCO with the modulation signal, and feeds back the reference clock subjected to the SSC modulation to the clock recovery unit.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: Aspects of systems, methods, algorithms, and non-transitory media storing computer-readable instructions for segmenting data processing workflows are provided. In a first aspect, a computer-implemented method for segmenting data processing workflows includes determining a configuration of an instrument system. The instrument system can include an analytical instrument coupled with an instrument PC (IPC). The IPC can be configured to receive raw data from the analytical instrument, to process the raw data, and to communicate with a client computing device coupled with the instrument system. The method can also include segmenting a data process workflow based at least in part on the configuration, attributing at least a subset of constituent operations of the data process workflow to the client computing device or the IPC.

Abstract: Methods and systems and systems provide for temperature control between thermoelectric coolers (TECs or TEMs) in a stack of multiple TECs, by optimizing the power suppled to each TEC in the stack. The temperatures may be continuously monitored, to continuously provide for the aforementioned power optimization.

Abstract: According to certain embodiments, an electronic device comprises: a battery; an interface module; a detection module electrically connected with the interface module, the detection module configured to detect than an external electronic device for receiving power is connected to the interface module; a protection module electrically connected with the interface module and comprising a first switching element; and a charging module electrically connected with the protection module, the detection module, and the battery, and comprising a voltage conversion circuit and a second switching element, the charging module configured to provide a first power to the protection module when the detection module detects connection of the external electronic device, wherein the first switching element is configured to turn on after receiving the first power, wherein the charging module is configured to raise a power from the battery to a designated value through the voltage conversion circuit, thereby resulting in a second

Abstract: An electronic apparatus including a power generation module including a power generation unit and a battery configured to store power generated by the power generation unit, a detection device, a drive unit including a plurality of circuits including a circuit configured to output a voltage to the detection device based on the power of the power generation module, a second capacitor unit electrically coupled in parallel to the battery, and a portable housing configured to accommodate the power generation module, the detection device, the drive unit, and the second capacitor unit.

Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.

Abstract: A frame synchronization apparatus according to an embodiment includes a reception unit, a frame memory, a time generation unit, a reception time acquisition unit, a timestamp acquisition unit, and a control unit. The reception unit is configured to receive packet data including video data and a timestamp. The frame memory is configured to store the packet data. The time generation unit is configured to generate a time based on a reference synchronization signal. The reception time acquisition unit is configured to acquire a reception time of packet data satisfying a condition based on the time. The timestamp acquisition unit is configured to acquire a timestamp from the packet data satisfying the condition. The control unit is configured to read packet data from the frame memory in accordance with a variation in a difference between the reception time and a time indicated by the timestamp.

Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

Abstract: A method of resetting an integrated circuit, includes: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.

Abstract: Disclosed is a hierarchical management method and system for a terminal device. The terminal device comprises at least one control system, and at least one peripheral apparatus, which is connected to the control system. In the method, when a terminal device receives a wake-up signal during dormancy, a control system corresponding to the wake-up signal is woken up, and the control system in a wake-up state grades an operation mode of the control system according to a data load; and according to the operation mode, a peripheral apparatus that needs to perform data processing is woken up.

Abstract: According to an embodiment, a method, performed by an electronic device, of providing a ranging-based service may include: transmitting, from a service application installed in the electronic device to a framework, information related to service data, the information related to the service data including a service deployment case and information about a storage location of the service data; when the electronic device approaches a reader device, receiving first data from the reader device; setting up a secure channel with the reader device by using information stored in a common applet identified based on the first data, the common applet being installed in a secure component of the electronic device; and transmitting the service data to the reader device, based on second data received from the reader device.

Abstract: An information handling system of an orchestrating Internet of Things (IoT) gateway executing a carbon dioxide (CO2) minimizing IoT edge gateway data processing orchestration system comprises a network interface device receiving processed IoT sensor data generated by alteration of unprocessed IoT sensor data via access point (AP) IoT servers executing a common data processing method, a processor executing code instructions to determine that an initial volume of CO2 emitted per unit of processed sensor data transferred from the AP IoT servers to a cloud platform, via the orchestrating IoT gateway in an enterprise wide area network, is greater than an adjusted volume of estimated CO2 that would be emitted per unit of data if the common data processing method were performed at the orchestrating IoT gateway instead of the AP IoT servers, and transmitting an instruction to cease execution of the common data processing method at the AP IoT servers.