Abstract: According to certain embodiments, an electronic device comprises: a battery; an interface module; a detection module electrically connected with the interface module, the detection module configured to detect than an external electronic device for receiving power is connected to the interface module; a protection module electrically connected with the interface module and comprising a first switching element; and a charging module electrically connected with the protection module, the detection module, and the battery, and comprising a voltage conversion circuit and a second switching element, the charging module configured to provide a first power to the protection module when the detection module detects connection of the external electronic device, wherein the first switching element is configured to turn on after receiving the first power, wherein the charging module is configured to raise a power from the battery to a designated value through the voltage conversion circuit, thereby resulting in a second

Abstract: An electronic apparatus including a power generation module including a power generation unit and a battery configured to store power generated by the power generation unit, a detection device, a drive unit including a plurality of circuits including a circuit configured to output a voltage to the detection device based on the power of the power generation module, a second capacitor unit electrically coupled in parallel to the battery, and a portable housing configured to accommodate the power generation module, the detection device, the drive unit, and the second capacitor unit.

Abstract: A workload dependent load-sharing mechanism in a multi-battery system. The mechanism is an energy management system that operates in three modes—energy saving mode, balancer mode, and turbo mode. The energy saving mode is a normal mode where the multiple batteries provide power to their own set of loads with least resistive dissipation. In balancing mode, the batteries are connected through switches operating in active mode so that the current shared is inversely proportion to the corresponding battery state-of-charge. In turbo mode, both batteries are connected in parallel through switches (e.g., on-switches) to provide maximum power to a processor or load. A controller optimizes the sequence and charging rate for a hybrid battery to maximize both the charging current and charging speed of the battery, while enabling longer battery life. The hybrid battery comprises a fast charging battery and a high-energy density battery.

Abstract: A frame synchronization apparatus according to an embodiment includes a reception unit, a frame memory, a time generation unit, a reception time acquisition unit, a timestamp acquisition unit, and a control unit. The reception unit is configured to receive packet data including video data and a timestamp. The frame memory is configured to store the packet data. The time generation unit is configured to generate a time based on a reference synchronization signal. The reception time acquisition unit is configured to acquire a reception time of packet data satisfying a condition based on the time. The timestamp acquisition unit is configured to acquire a timestamp from the packet data satisfying the condition. The control unit is configured to read packet data from the frame memory in accordance with a variation in a difference between the reception time and a time indicated by the timestamp.

Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

Abstract: A method of resetting an integrated circuit, includes: generating, in response to a reset signal intended for a first data unit, a synchronous reset signal based on the reset signal, and outputting the synchronous reset signal to the first data unit after at least one preset period; and generating, in response to a first data signal output by the first data unit, a second data signal based on the synchronous reset signal and the first data signal, and outputting the second data signal to a second data unit. An integrated circuit is also provided.

Abstract: Disclosed is a hierarchical management method and system for a terminal device. The terminal device comprises at least one control system, and at least one peripheral apparatus, which is connected to the control system. In the method, when a terminal device receives a wake-up signal during dormancy, a control system corresponding to the wake-up signal is woken up, and the control system in a wake-up state grades an operation mode of the control system according to a data load; and according to the operation mode, a peripheral apparatus that needs to perform data processing is woken up.

Abstract: According to an embodiment, a method, performed by an electronic device, of providing a ranging-based service may include: transmitting, from a service application installed in the electronic device to a framework, information related to service data, the information related to the service data including a service deployment case and information about a storage location of the service data; when the electronic device approaches a reader device, receiving first data from the reader device; setting up a secure channel with the reader device by using information stored in a common applet identified based on the first data, the common applet being installed in a secure component of the electronic device; and transmitting the service data to the reader device, based on second data received from the reader device.

Abstract: An information handling system of an orchestrating Internet of Things (IoT) gateway executing a carbon dioxide (CO2) minimizing IoT edge gateway data processing orchestration system comprises a network interface device receiving processed IoT sensor data generated by alteration of unprocessed IoT sensor data via access point (AP) IoT servers executing a common data processing method, a processor executing code instructions to determine that an initial volume of CO2 emitted per unit of processed sensor data transferred from the AP IoT servers to a cloud platform, via the orchestrating IoT gateway in an enterprise wide area network, is greater than an adjusted volume of estimated CO2 that would be emitted per unit of data if the common data processing method were performed at the orchestrating IoT gateway instead of the AP IoT servers, and transmitting an instruction to cease execution of the common data processing method at the AP IoT servers.

Abstract: Systems and techniques are provided for booting an electronic device. For example, a process can include initiating a boot procedure for the electronic device. The process can also include determining a hardware pseudo-random number generator (PRNG) is inoperable, obtaining a seed value from a read-only memory, based on the determination that the hardware PRNG is inoperable, initiating a software PRNG based on the seed value, obtaining a pseudo-random number from the software PRNG, and continuing the boot procedure using the obtained pseudo-random number.

Abstract: Methods and systems for managing operation of data processing systems are disclosed. To manage operation of the data processing systems, the data processing systems may present unified communication and management systems. The unified communication and management systems may be used to manage the operation of any number of management controller embedded devices hosted by the data processing systems. The unified communication and management systems may allow for communication with and management of the management controller embedded devices without requiring that the management systems directly interact with the management controller embedded devices.

Abstract: A method for partitioning executable operations for a reconfigurable computing system includes receiving a set of expressions comprising a plurality of operations and dependencies for those operations, partitioning the plurality of operations into selected executable partitions wherein each selected executable partition conforms to resource constraints for a reconfigurable unit of the reconfigurable computing system. Partitioning the plurality of operations into selected executable partitions may include seeding a candidate partition with an operation, recursively generating an additional candidate partition for each operation adjacent to the candidate partition whose dependent operations are already within the candidate partition or a previously selected partition, and selecting a best candidate partition based on resource cost. A corresponding system and computer-readable medium are also disclosed herein.

Abstract: Systems and methods are disclosed for a multiphase clock generation. An example method includes facilitating, by a phase interpolator (PI) circuit comprising a plurality of PIs, transfer of information across one or both of a transmit (TX) lane or a receive (RX) lane, wherein the transfer of information is based on a clock timing. The PI circuit receives, from a clock-and-data recovery (CDR) circuit, a plurality of input clock phases. The CDR circuit comprises a centrally located phase-locked loop (PLL) circuit and a plurality of multiphase generators. In some embodiments, each multiphase generator of the plurality of multiphase generators is adjacent to a respective PI of the plurality of PIs. Based on the plurality of input clock phases, the PI circuit adjusts, the clock timing for the transfer of information.

Abstract: Disclosed are devices and methods, among which is a pattern-recognition processor coupled to a microcontroller. The pattern-recognition processor may act as a peripheral device to the microcontroller and provide supplemental pattern recognition functionality to the existing functionality of the microcontroller.

Abstract: A storage controller implemented on a System On Chip (SOC) includes an upstream functional module, a host interface, a logical to physical (L2P) interface, and a message inspection engine. The configured message inspection engine is obtained using one or more configuration settings and receives an input message from the upstream functional module. The input message is analyzed to determine a retention plan, a content modification plan, and a destination control plan. An output message is generated based at least in part on the input message, the content modification plan, and the destination control plan. If there is an affirmative content modification decision, the output message is populated with content absent from the input message. If there is an affirmative destination modification decision, the output message is populated with a destination absent from the input message. The output message is output unless there is an affirmative retention decision.

Abstract: If a first group selection setting is set to TRUE, an NVM Express (NVMe) processor sends a first set of NVMe status information that includes a transfer data end event. If a second group selection setting is set to TRUE, the NVMe processor sends a second set of NVMe status information that includes an NVMe error event. A firmware functional module sends firmware status information. The aggregation module aggregates and timestamps the first and second sets of NVMe status information, if any, and the firmware status information to obtain a timestamped and aggregated message stream that is output by an interface. The timestamped and aggregated message stream enables a visualization system to analyze the NVMe processor and the firmware functional module. The NVMe processor, firmware functional module, aggregation module, and interface are in a storage controller, implemented on a system on chip (SOC), that manages a storage medium.

Abstract: Exemplary embodiments maintain spatial locality of the data being processed by a sparse CNN. The spatial locality is maintained by reordering the data to preserve spatial locality. The reordering may be performed on data elements and on data for groups of co-located data elements referred to herein as “chunks”. Thus, the data may be reordered into chunks, where each chunk contains data for spatially co-located data elements, and in addition, chunks may be organized so that spatially located chunks are together. The use of chunks helps to reduce the need to re-fetch data during processing. Chunk sizes may be chosen based on the memory constraints of the processing logic (e.g., cache sizes).

Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

Abstract: A memory module mounting apparatus for coupling a memory module to a processor of an information handling system includes a z-axis compression connector and a compression connector mount. The z-axis compression connector has first compression contacts on a first surface of the compression connector and second compression contacts on a second surface of the compression connector. The first compression contacts couple the compression connector to the processor. The compression connector mount has contact pads on a first surface of the compression connector mount. The first contact pads couple the compression connector mount to the first compression contacts, and have contact elements configured to couple the contact pads to the memory module.

Abstract: An example memory apparatus includes clock circuitry. The clock circuitry can generate first and second clock signals based on a system clock signal, with the first and second clock signals being mutually out of phase. The apparatus can include detection circuitry to provide a detection result indicating whether an initial operation of a self-refresh exit operation coincides with a rising edge of the first clock signal or a rising edge of the second clock signal. The apparatus can include processing circuitry to provide an odd clock signal and an even clock signal based first and second clock signals and the detection result. The processing circuitry can provide the odd clock signal and the even clock signal out of phase or in phase with the first clock signal and the second clock signal depending on the detection result.