Patents Examined by Raymond N Phan
  • Patent number: 11657014
    Abstract: Signal bridging using an unpopulated processor interconnect, including: communicatively coupling an apparatus to a plurality of first signal paths between a bootstrap processor (BSP) and a processor interconnect of a circuit board; communicatively coupling the apparatus to a plurality of second signal paths between the processor interconnect and a peripheral interface of the circuit board; and communicatively coupling the BSP to the peripheral interface via one or more third signal paths in the apparatus.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: May 23, 2023
    Inventor: Jason R. Talbert
  • Patent number: 11640366
    Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 2, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Dan Saad, Guy Nakibly, Yaniv Shapira, Aviv Bonomo, Moshe Gutman
  • Patent number: 11625350
    Abstract: A control system for a process or manufacturing installation includes a first and second operator station servers, wherein one operator station server operates as master and the other of operates as slave that inherits master functionality when the master fails, respective data archives are implemented on the first and second operator station servers, the first and second operator station servers each receive data of the technical installation and record it in the respective data archive, and the first and second operator station servers each ascertain a respective health state, where the first and second operator station servers continuously record in the respective data archive, at specified time intervals, which health state the respective operator station server has when receiving and recording the data of the technical installation, and whether the respective operator station server acts as master or as slave in the respective time interval.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: April 11, 2023
    Inventor: Benjamin Lutz
  • Patent number: 11619963
    Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Amir Javidi, Daniel Cummings, Glenn Starnes
  • Patent number: 11615036
    Abstract: In a method and system for identifying addresses of slave devices, the system includes a main board, slave devices, and a power source. The main board is electrically connected to the slave devices and a delay unit is set in each slave device. An output terminal of the delay unit is electrically connected to the main board. The delay unit outputs a delay signal to the main board when first powered on, the main board receives the delay signal, computes a delay time of the delay signal, and by reference to a preset table identifies the slave device based on the specific delay time. Occupation of input and output I/O pins is reduced, a device for identifying addresses of slave devices is also disclosed.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 28, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Xiao-Long Zhou
  • Patent number: 11615040
    Abstract: A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Geet Govind Modi, Sumantra Seth, Subhashish Mukherjee
  • Patent number: 11609769
    Abstract: A reconfigurable data processor comprises a bus system, and an array of configurable units connected to the bus system, configurable units in the array including configuration data stores to store unit files comprising a plurality of sub-files of configuration data particular to the corresponding configurable units. Configurable units in the plurality of configurable units each include logic to execute a unit configuration load process, including receiving via the bus system, sub-files of a unit file particular to the configurable unit, and loading the received sub-files into the configuration store of the configurable unit. A configuration load controller connected to the bus system, including logic to execute an array configuration load process, including distributing a configuration file comprising unit files for a plurality of the configurable units in the array.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 21, 2023
    Assignee: SambaNova Systems, Inc.
    Inventors: Manish K. Shah, Ram Sivaramakrishnan, Mark Luttrell, David B. Jackson, Raghu Prabhakar, Sumti Jairath, Gregory Frederick Grohoski, Pramod Nataraja
  • Patent number: 11604505
    Abstract: Various embodiments include methods and devices for system on chip infrastructure of system on chip infrastructure secure memory access and power management. Some embodiments, include determining whether a processor is performing a secure memory access transaction, and gating a clock signal from being transmitted to a secure portion of a memory in response to determining that the processor is not performing a secure memory access transaction. Some embodiments include determining whether any processor is operating in a secure mode, and transmitting a retention signal to the secure portion of the memory in response to determining that no processor is operating in a secure mode. The retention signal may be configured to set a retention state for the secure portion of the memory.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 14, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Bharat Kumar Rangarajan, Rajesh Arimilli, Rengarajan Ragavan
  • Patent number: 11599141
    Abstract: A synchronizing system including a generation unit for generating a synchronizing pulse from data of an independent clock, the synchronizing pulse being generated in a periodic manner, transmission links to transmit the synchronizing pulse to all the computation units, and in each of the computation units, a control element to compare the synchronizing pulse that has been received to a pulse generated by an internal clock of the computation unit and to detect a compliance or a lack of compliance, a scheduler of each of the computation units activating a sequence of partitions when the synchronizing pulse is received, and this only if the control element has detected a compliance. The synchronizing system is configured to synchronize the computation units in a reliable and accurate manner and to increase the operating safety of these computation units.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: March 7, 2023
    Inventors: Christophe Vlacich, Bertrand Deshayes, Frédéric Viader, Laurent Lafont
  • Patent number: 11599439
    Abstract: A universal device identifier (UDID) service with adjusted attribute distances. In one embodiment, a server includes an electronic processor and a memory storing the UDID service. The electronic processor is configured to receive an identification request regarding a currently-observed device having a first set of device attributes, retrieve any previously-observed devices, determine whether one or more devices are found from retrieving the any of the previously-observed devices, determine all changed device attributes for each device of the one or more devices that are found relative to the first set of device attributes, generate an adjusted attribute distance corresponding to the all changed device attributes for the each device, retrieve a universal device identifier (UDID) of a closest device having a lowest adjusted attribute distance among all adjusted attribute distances that are generated, and assign the UDID of the closest device to the currently-observed device.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: March 7, 2023
    Inventors: Igor Opushnyev, John Hearty, Anton Laptiev
  • Patent number: 11599485
    Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: March 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Reshmi Basu, Jonathan S. Parry
  • Patent number: 11593158
    Abstract: A universal peripheral extender architecture, system, and method is disclosed that addresses the need of communicatively connecting peripheral I/O devices and the smart host devices in legacy, medical, and industrial applications. As disclosed, a universal peripheral extender includes an I/O device translation & management module that has a device-side utility, a host-side I/O device translation & management utility, and a host/device translation & management scheduler utility.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: February 28, 2023
    Inventor: Ben Wei Chen
  • Patent number: 11580053
    Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: February 14, 2023
    Inventors: Win Naing Maung, Suzanne Mary Vining, Yonghui Tang, Douglas Edward Wente, Huanzhang Huang
  • Patent number: 11579876
    Abstract: A method of save-restore operations includes monitoring, by a power controller of a parallel processor (such as a graphics processing unit), of a register bus for one or more register write signals. The power controller determines that a register write signal is addressed to a state register that is designated to be saved prior to changing a power state of the parallel processor from a first state to a second state having a lower level of energy usage. The power controller instructs a copy of data corresponding to the state register to be written to a local memory module of the parallel processor. Subsequently, the parallel processor receives a power state change signal and writes state register data saved at the local memory module to an off-chip memory prior to changing the power state of the parallel processor.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: February 14, 2023
    Assignees: Advanced Micro Devices, Inc., ATI TECHNOLOGIES ULC
    Inventors: Anirudh R. Acharya, Alexander Fuad Ashkar, Ashkan Hosseinzadeh Namin
  • Patent number: 11579995
    Abstract: An electronic element includes: a module for storing reference data; a module for receiving data from a processor; a module for verifying the received data by comparison by way of reference data; and a module for transmitting an instruction to cut off supply of the processor, the supply cutoff instruction being transmitted after occurrence of a failure event, the failure event being an absence of reception of data or a failure in verifying the data. A system including such an electronic element and a method for monitoring a processor by the electronic element are also described.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: February 14, 2023
    Assignee: IDEMIA FRANCE
    Inventors: Sylvestre Denis, Emmanuelle Dottax
  • Patent number: 11567887
    Abstract: Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: January 31, 2023
    Inventors: Ryan Black, Todd Alan Greenfield, Timothy Lindquist
  • Patent number: 11567561
    Abstract: An energy-aware system is provided. The system includes an energy harvester adapted to supply harvested energy as an output for storage at an energy storage; and a scheduler, the scheduler being made up of, at least in part, hardware of the energy-aware system, the scheduler operable to schedule execution of operations performed by the energy-aware system, wherein the scheduler is configured to: determine if a current voltage level at the energy storage is higher than a start voltage level; and cause initiation of execution of at least a portion one of the operations when the start voltage of the one of the operations levels is lower than or equal to the current voltage level.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: January 31, 2023
    Assignee: Wiliot, Ltd.
    Inventors: Yaron Elboim, Dotan Ziv, Yuval Amran, Nir Shapira
  • Patent number: 11561765
    Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 24, 2023
    Assignee: Intel Corporation
    Inventors: John Howard, Steven B. McGowan, Krzysztof Perycz
  • Patent number: 11544210
    Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: January 3, 2023
    Inventors: Meng Kun Lee, Priyanka Nilay Thakore, Chen Xiu, Lyle E. Adams, Xiaojun Ding
  • Patent number: 11544159
    Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: January 3, 2023
    Assignee: Apple Inc.
    Inventors: Alexander Paley, Andrew W. Vogan, Tudor Antoniu