Abstract: A method of operating a plurality of driving units for powering electronic units is described. The method includes interchanging a data frame including a bit sequence, between a master control unit and at least one of a plurality of driving units at slave nodes. The method includes applying an ID field for addressing at least one driving unit, and applying a data field comprising information and/or instructions regarding the status of the electronic units. Applying the ID field comprises indicating the driving unit address using a first bit sub-string comprising N bits, allowing the master control unit to identify whether data should be received or transmitted, performing a data length decoding step, and adding a further bit string to the data field including information for carrying out an action by the driving unit.

Abstract: Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

Abstract: A method is disclosed for project support in using an electric appliance with a battery pack. The method includes storing project data relating to at least a part of a sequence of project steps on a data storage of the battery pack, wherein the project data includes, for each project step, associated user information. For a predetermined project step of the sequence of project steps, the associated user information is output in visual and/or acoustic form by means of an output device of the battery pack. The user information and/or further user information for the predetermined project step are output in visual and/or acoustic form and/or provided for retrieval by a user by means of at least one external computing unit.

Abstract: A power over Ethernet (PoE) power supplying method where power sourcing equipment (PSE) and a powered device exchange link layer discovery protocol data units (LLDPDUs). Each of the LLDPDUs includes two power values. Each of the power values indicates requested or allocated power for one of two sets of cable pairs of the Ethernet twisted pair connecting the PSE and the powered device. Accordingly, the supplied powers to the powered device at sets of cable pairs are independent from each other.

Abstract: A thread executing a task at a node in a multi-socket computing system may access a first data structure to obtain a first calibration dataset for the node. The first thread may generate a timestamp based on the first calibration dataset and a first quantity of time measured by a clock at the first node. The real-time duration of the task may be determined based on the timestamp. The first thread may recalibrate the first clock by at least generating, based on the first quantity of time measured by the clock and a second quantity of time measured by a wall clock of an operating system of the multi-socket computing system, a second calibration dataset. The first thread may update the first data structure to include the second calibration dataset while a second thread accesses a second data structure to obtain calibration data.

Abstract: The present invention provides a memory structure, which is disposed on a first circuit board and connected electrically to a system power supply of a second circuit board. The memory structure comprises a plurality of memory unit, a power control component, and a display component. The power control component receives a first voltage of the system power supply. The power control component includes a power management unit and a linear voltage stabilizing unit. The display component includes a light-emitting unit and a control unit. The power control component provides a second voltage to the plurality of memory units using the power management unit. The linear voltage stabilizing unit provides a third voltage to the light-emitting unit and the control unit. The power management unit distributes the power supply to the plurality of memory units, the light-emitting unit, and the control unit for further usage.

Abstract: A system-on-chip (SoC) in which trace data is managed includes a first memory device, a first interface to couple the first memory to a second memory external to the system-on-chip, and a first processing resource coupled to the first interface and the first memory device. The first processing resource includes a data buffer and a first direct access memory (DMA) controller. The first DMA controller transmits data from the data buffer to the first interface over a first channel, and transmits the data from the data buffer with associated trace information for the data to the first memory device over a second channel.

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

Abstract: A user device (24) includes an audio output device (58) and one or more processors (44). The one or more processors are configured to run an Operating System (OS-48), including running an OS component for coordinating outputting of audio generated by user applications (26) to the audio output device, to preload a user application, and, while the user application is in a preload state, to inhibit the audio generated by the preloaded user application using the OS component.

Abstract: The present disclosure is directed to a power supply to drive a consumer component, which is operable in any one of multiple power states in a specified duration. The power supply contains a phase controller and power stage, to together drive the consumer component to a desired power state in a corresponding duration. According to an aspect, the phase controller includes a pin, an impedance network and an internal controller. The impedance network is configurable by the internal controller to provide a first impedance at the pin when the desired power state is a first power state and a second impedance when the desired power state is a second power state. Accordingly, the power stage may source an electrical signal to the pin and sense the response to determine whether the desired power state is the first or the second power state.

Abstract: Embodiments of the invention may provide an improved method for pre-heating an electronic device such as an information handling system, when internal temperatures are below safe operating ranges. To do so, the system selectively heats the entire device or select zones of the electronic device for a predetermined amount of time when the system is restarted after a period of time sufficient to bring the system to ambient temperatures. The predetermined amount of time is determined based on measured ambient temperatures. Using a table that corresponds the ambient temperatures to a time that a component needs to heat up to a nominal temperature in a zone, the predetermined time can be calculated.

Abstract: An integrated circuit includes a memory configured to store a plurality of functions; a mapping interface configured to perform a mapping from a received first signal to a first function of the plurality of functions; and a state machine configured to, in response to said mapping, execute the first function; wherein the integrated circuit is arranged to, in dependence on the execution of the first function at the state machine, modify said mapping between the first signal and the first function so as to re-map the first signal to a second function of the plurality of functions such that, on receiving a subsequent first signal, the state machine is configured to execute the second function.

Abstract: Methods, systems, and devices for error information storage for boot-up procedures are described. A memory system may detect an error associated with performing the boot-up procedure of the memory system and may store error information associated with the detected error in a persistent register at the memory system. In some cases, the memory system may additionally store the error information in a cache at the memory system. After storing the error information, the memory system may reset and, after resetting, may transfer the error information from the persistent register to a non-volatile memory device at the memory system. In cases that the memory system stores error information in the cache prior to the reset, the memory system may additionally transfer the error information from the cache to the non-volatile memory device.

Abstract: An apparatus and method coupling a first and a second data bus comprising selectors for routing first bus egress lanes to egress memories, each egress memory coupled to one second bus egress lane, where the second bus has more egress lanes than the first. Each egress memory corresponds to one second bus egress lane. A first FSM selecting which first bus egress lane to load into each egress memory synchronous with the first bus clock. A second FSM outputting egress memory values to the second bus synchronous with the second bus clock. A set of ingress memories, each memory coupled to one second bus ingress lane and to an input of each ingress selector. A third FSM loading the ingress memories synchronous with the second bus clock. A fourth FSM selecting which ingress memory to route to each first bus ingress lane synchronous with the first bus clock.

Abstract: A non-transitory computer-readable storage medium may be executable by a processor to receive a designation of a message bus producer, a set of business logic to be stored in a set of containers, a designation of a message bus consumer, and a designation of a set of message-handling functions. The non-transitory computer-readable storage medium may generate a serverless application stack, based upon the message bus producer, the set of business logic, the message bus consumer, and the set of message-handling functions. The non-transitory computer-readable storage medium may cause the serverless application stack to receive a message stream from the message bus producer as streaming data, process the message stream according to at least one function, stored in the set of containers, perform at least one message-handling function of the set of message-handling functions on the message stream, and transport the set of messages to the message bus consumer.

Abstract: The present disclosure provides a synchronization signal generating circuit, a chip, and a synchronization method and a synchronization device, based on a multi-core architecture, configured to generate a synchronization signal for M node groups, wherein each of the node groups includes at least one node, and M is an integer greater than or equal to 1. The synchronization signal generating circuit includes: a synchronization signal generating sub-circuit and M group ready signal generating sub-circuits. The M group ready signal generating sub-circuits are in one-to-one correspondence with the M node groups. The synchronization signal generating sub-circuit generates a first synchronization signal based on the first to-be-started signal, wherein the first synchronization signal is configured to instruct the K nodes in the first node group to start synchronization.

Abstract: Embodiments herein describe using an adaptive chip-to-chip (C2C) interface to interconnect two chips, wherein the adaptive C2C interface includes circuitry for performing multiple different C2C protocols to communicate with the other chip. One or both of the chips in the C2C connection can include the adaptive C2C interface. During boot time, the adaptive C2C interface is configured to perform one of the different C2C protocols. During runtime, the chip then uses the selected C2C protocol to communicate with the other chip in the C2C connection.

Abstract: A power source supply control device supplies electric power to independent loads from a common main power source or main power sources. The control device includes: switch units configured to switch electric power supply to the loads from the main power source; a plurality of power source monitor units each configured to monitor a power source state in each of power source lines at a downstream side of the switch units; and a switch control unit configured to control each of the switch units sequentially. The switch control unit specifies a switching order to the loads according to a predetermined state, and switches the switch unit that controls energization to a second load, after a power source meets a predetermined condition, based on output of the power source monitor unit that monitors electric power supply to a first load whose switching order is earlier than the second load.

Abstract: In one embodiment, a method includes transmitting power in a power and data distribution system comprising at least two pairs of wires, negotiating a power level between Power Sourcing Equipment (PSE) and a Powered Device (PD) in the power and data distribution system, transmitting the power at a power level greater than 100 watts, periodically checking each of the wires for a fault, and checking for an electrical imbalance at the wires.

Abstract: A virtual function (VF) of a virtual machine is enabled to directly reset a processing portion of a processing unit. The VF initiates the reset of the processing portion directly and a host driver associated with the processing unit is bypassed during the reset process. By allowing for a direct reset of the processing portion, a processing system reduces the overhead associated with the reset process, enhances system security, and improves overall VM and hardware isolation at the processing system.