Patents Examined by Raymond N Phan
  • Patent number: 10698843
    Abstract: An interconnect circuit includes a plurality of input interfaces and a plurality of output interfaces. A plurality of source devices are respectively coupled to the input interfaces. A target device has a plurality of access ports respectively coupled to the output interfaces. Each source device is configured to deliver transactions to the target device. Programmable control circuit is configured to deliver, to the interconnect circuit, a control word designating an access port assigned to this source device. The interconnect circuit is configured to route the transaction from the corresponding input interface to the output interface that is coupled to this access port and to deliver the transaction to the access port, the content of each transaction delivered to an access port being identical to the content of the corresponding transaction delivered by the source equipment whatever the selected access port.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: June 30, 2020
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Yassine El Khourassani, Patrick Valdenaire, Emmanuel Ardichvili
  • Patent number: 10691506
    Abstract: Systems and methods for managing locks in a data acquisition system with a distributed data storage are disclosed. In embodiments, a storage node of a data acquisition system with a plurality of storage nodes receives a request for an unprocessed event, where portions of the event data are stored across the plurality of storage nodes. One node of the plurality of nodes holds the lock value for the event. The node receiving the request searches for an event where it stores the lock value that is unlocked. If none is found, the node receiving the request forwards the request to a second node, which repeats the search.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Jakub Radtke, Pawel Makowski, Maciej Maciejewski, Pawel Lebioda, Piotr Pelplinski, Aleksandra Wisz
  • Patent number: 10684967
    Abstract: A unit for managing initial saving, subsequent saving, and reading technical information such as plans, figures, executed works, manuals, notebooks, a visitors' book, maintenance records, and the like of a site such as a building, a ship, a platform, an industrial facility, and the like, the unit comprising a casing incorporating an electronic circuit comprising a non-volatile memory, a USB connector and a processor controlled by firmware controlling the management of inputs and outputs and of the memory, wherein the firmware comprises means for managing the inputs-outputs according to the standard USB protocol, and in addition for preventing the change command from modifying information previously recorded in the non-volatile memory.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 16, 2020
    Assignee: E-GLOO DEVELOPMENT
    Inventors: Bernard Blanchet, Edouard De Ledinghen, Lionel Laurent
  • Patent number: 10678727
    Abstract: A method for processing network data traffic includes obtaining a first distributed structure corresponding to a program based on a first storage structure, wherein the program is configured to process network data traffic; dividing a network device based on a second storage structure into a plurality of execution units, wherein the plurality of execution units is configured to execute the program; mapping the first distributed structure and the plurality of execution units to obtain a second distributed structure; and controlling the plurality of execution units to process network data traffic based on the second distributed structure.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 9, 2020
    Assignee: HILLSTONE NETWORKS CORP.
    Inventors: Dongyi Jiang, Linyang Shu, Jiangbo Nie, Ye Zhang, Yu Jia, Qijun Yang, Juxi Li
  • Patent number: 10678494
    Abstract: Systems and methods for using distributed Universal Serial Bus (USB) host drivers are disclosed. In one aspect, USB packet processing that was historically done on an application processor is moved to a distributed USB driver running in parallel on a low-power processor such as a digital signal processor (DSP). While a DSP is particularly contemplated, other processors may also be used. Further, a communication path is provided from the low-power processor to USB hardware that bypasses the application processor. Bypassing the application processor in this fashion allows the application processor to remain in a sleep mode for longer periods of time instead of processing digital data received from the low-power processor or the USB hardware. Further, by bypassing the application processor, latency is reduced, which improves the user experience.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: June 9, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Amit Gupta, Andrew Cheung, Ameya Kulkarni, Hemant Kumar
  • Patent number: 10664191
    Abstract: Systems and methods for providing input/output (I/O) determinism. An I/O instruction and at least one service level indicator are received, wherein the at least one service level indicator includes a required time for executing the I/O instruction. It is determined whether the I/O instruction can be executed on the storage within the required time. When it is not determined that the I/O instruction can be executed on the storage within the required time, a notification is sent.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 26, 2020
    Assignee: Excelero Storage Ltd.
    Inventors: Yaniv Romem, Omri Mann, Ofer Oshri
  • Patent number: 10656702
    Abstract: To keep up with achievement of the TEC value and suppressing the wear-out of hardware. An image forming apparatus of the present disclosure, which is configured to transit, after an elapse of a sleep-transition time, to enter a power-saving state in which power supply destinations are limited when compared to a normal state, includes a power amount prediction unit and an extension control unit. The power amount prediction unit acquires, whenever a state-transition is made, a power-consumption amount during an immediate preceding power-saving state to calculate a predicted power-consumption amount in a specific period based on the power-consumption amount. The extension control unit gives priority to the sleep-transition to enter the power-saving state if the predicted power-consumption amount exceeds the TEC value corresponding to the specific period, while extends the sleep-transition time if the predicted power-consumption amount fails to exceed the TEC value corresponding to the specific period.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: May 19, 2020
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Yukihiro Shibata
  • Patent number: 10649931
    Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 12, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Gerd Dirscherl, Benedikt Driessen, Gunther Fenzl, Franz Klug, Bernd Meyer, Steffen Sonnekalb
  • Patent number: 10649945
    Abstract: Disclosed herein are systems and techniques for digital interfaces over a two-wire communication bus. For example, an electronic device to interface between a two-wire communication bus and a non-native digital interface may include: a digital interface to support a first digital interface protocol; and a transceiver, coupled to the digital interface, to couple to a link of the two-wire communication bus and to receive data via the link, wherein the data includes commands in accordance with a second digital interface protocol different from the first digital interface protocol; wherein the digital interface is to transmit the commands to a peripheral device in accordance with the second digital interface protocol.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: May 12, 2020
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Philip Gregory Geerling, Eric Zolner, Martin Kessler, Peter Sealey
  • Patent number: 10642659
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating compute units is presented that includes forming compute units among a plurality of physical computing components comprising at least central processing units (CPUs), storage modules, and network interface modules coupled over a Peripheral Component Interconnect Express (PCIe) fabric configured to communicatively couple the plurality of physical computing components and isolate the compute unit in the clustered environment using logical partitioning within the PCIe fabric. The method also includes initiating a software component deployed to at least associated CPUs within the compute units, reporting telemetry to the management processor related to operation of the compute unit, and emulating operation of an Ethernet interface to an operating system of the associated CPU for transfer of communications comprising at least the telemetry to the management processor over the PCIe fabric.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: May 5, 2020
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Christopher R. Long, James Scott Cannata
  • Patent number: 10635626
    Abstract: A connecting method includes the following operations: storing a plurality of MAC addresses by a memory of a docking station; determining a first MAC address of the plurality of MAC addresses by a processor of a docking station, wherein the first MAC address is corresponding to a first electronic device of the plurality of electronic device; establishing a BLUETOOTH connection between the first electronic device and the docking station by the processor; establishing a USB connection or Bluetooth connection between the docking station and a computer by the processor; and pairing the computer and the first electronic device through the docking station.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 28, 2020
    Assignee: I/O INTERCONNECT, LTD.
    Inventors: Gary Kung, Ping-Shun Zeung
  • Patent number: 10628364
    Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hojun Shim
  • Patent number: 10628360
    Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Manabu Koike
  • Patent number: 10621125
    Abstract: A packet processing device is connected as a route of a plurality of I/O devices and configures a PCIe fabric. The packet processing device includes a plurality of first request processing units and a second request processing unit that process a PCIe packet issuing request to the I/O device; and a first selecting unit that selects the plurality of first request processing units or the second request processing unit, based on a request classification of the PCIe packet issuing request, and a load exerted on the PCIe fabric by a packet to be transmitted to the I/O device. The first selecting unit includes a first determining unit that determines whether the PCIe packet issuing request is possible to pass another PCIe packet issuing request being processed by the first request processing unit, based on a transaction identifier included in the PCIe packet issuing request.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: April 14, 2020
    Assignee: NEC CORPORATION
    Inventors: Akira Tsuji, Masaki Kan, Jun Suzuki, Yuki Hayashi
  • Patent number: 10613896
    Abstract: A computer-implemented method according to one embodiment includes identifying an input/output (I/O) operation to be implemented within a distributed computing environment, where the distributed computing environment executes a plurality of different jobs, determining information associated with the I/O operation indicating that the I/O operation is associated with a recovery of one of the plurality of different jobs, and assigning an implementation priority to the I/O operation, based on the information associated with the I/O operation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Subashini Balachandran, Lukas Rupprecht, Rui Zhang
  • Patent number: 10614008
    Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: April 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kyohei Yamaguchi, Daisuke Kawakami, Hiroyuki Hamasaki
  • Patent number: 10606497
    Abstract: Methods and systems for enhanced performance during reduced network functioning are provided. A system may include a path detection module that detects a path change in a plurality of paths, the plurality of paths communicatively couple a host device to a plurality of volumes. Further, the data is replicated from a pre-change primary volume in the plurality of volumes to a post-change primary volume in the plurality of volumes. The system also includes a replication direction module that switches a direction of replication in response to the detected path change. Additionally, the data is replicated from the post-change primary volume to the pre-change primary volume in response to the detected path change. The system further includes an activity module that determines an activity level associated with one or more extents and arranges the one or more extents on the post-change primary volume in response to the detected path change.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sarvesh Patel, Subhojit Roy, Kushal Patel
  • Patent number: 10592448
    Abstract: A master-slave system, a command execution method, and a data access method are provided. The master-slave system includes a master device and a slave device. The master device provides a first command and a clock signal to the slave device. The slave device executes a first operation corresponding to the first command according to the first command and the clock signal. When the first operation corresponding to the first command is completed, the slave device generates a response signal according to the clock signal to notify the master device an execution result of the first operation corresponding to the first command.
    Type: Grant
    Filed: January 21, 2019
    Date of Patent: March 17, 2020
    Assignee: Guangzhou Tyrafos Semiconductor Technologies Co., LTD
    Inventor: Keng-Li Chang
  • Patent number: 10592205
    Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 17, 2020
    Assignee: INTEL CORPORATION
    Inventors: John Howard, Steven B. McGowan, Krzysztof Perycz
  • Patent number: 10587252
    Abstract: A skew compensation circuit includes a common mode generator, a common mode comparator, a common mode detector, and a skew adjustment circuit. The common mode generator generates a common mode voltage according to a first input voltage and a second input voltage. The common mode comparator generates a first comparison voltage and a second comparison voltage according to the common mode voltage. The common mode detector generates a first control voltage, a second control voltage, a third control voltage, and a fourth control voltage according to the first comparison voltage, the second comparison voltage, a first data voltage, and a second data voltage. The skew adjustment circuit generates a first output voltage and a second output voltage according to the first data voltage, the second data voltage, the first control voltage, the second control voltage, the third control voltage, and the fourth control voltage.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 10, 2020
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventor: Yeong-Sheng Lee