Patents Examined by Raymond N Phan
  • Patent number: 10515046
    Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Kermin Fleming, Kent D. Glossop, Simon C. Steely, Jr.
  • Patent number: 10509751
    Abstract: In cases where local devices (6, 6a) support a master transfer function, a portion of the memory space, of each of local devices (6, 6a), to be controlled from system host (2) is mapped onto a memory space on system host (2) side and a plurality of local devices (6, 6a) are reconfigured as one virtual local device. This provides information processing apparatus (4) which, in cases of connection with the plurality of local devices (6, 6a), resolves resource shortage on system host (2) side by appropriately mapping necessary registers of local devices (6, 6a) onto a memory space for system host (2).
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: December 17, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Yamashita, Takeshi Ootsuka
  • Patent number: 10503240
    Abstract: A power supply architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller comprises a power rail, a VDDD terminal, a VCONN terminal, and a VBUS terminal. The VDDD terminal, the VCONN terminal, and the VBUS terminal are coupled to the power rail, where a VCONN switch is coupled between the VCONN terminal and the power rail, and a VBUS regulator is coupled between the VBUS terminal and the power rail. The power rail is coupled to internal circuits of the IC controller and is configured to provide operating power to the internal circuits from any one of the VCONN terminal and the VBUS terminal.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 10, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Nicholas Alexander Bodnaruk, Anup Nayak, Pavan Kumar Kuchipudi
  • Patent number: 10496580
    Abstract: In one or more embodiments, one or more systems, methods, and/or systems may provide an output signal via a first port of multiple ports; may determine that the output signal is detected via a second port of the multiple ports; if the first port and the second port are not capable of being coupled, may provide a notification that indicates that the first port and the second port are not capable of being coupled; and if the first port and the second port are capable of being coupled: may configure a Serializer/Deserializer (SerDes) associated with the first port to communicate with a SerDes associated with the second port; and may configure a first processor of multiple processors to communicate with a second processor of the multiple processors via the SerDes associated with the first port.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 3, 2019
    Assignee: Dell Products L.P.
    Inventors: Timothy M. Lambert, Jordan H. Chin, Jeffrey Leighton Kennedy
  • Patent number: 10496912
    Abstract: An electronic unit includes a communication interface, a processor, a secure element, and a sub-system. The processor is connected to the communication interface by a first bus, to the secure element by a second bus and to the sub-system. The processor is designed to operate in a first mode, in which, at the second bus, it reproduces the signals received from the communication interface at the first bus. Also disclosed is a method carried out in such an electronic unit.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: December 3, 2019
    Assignee: IDEMIA France
    Inventors: Nicolas Bousquet, Florian Vallee
  • Patent number: 10484732
    Abstract: Systems, devices, and methods according to the present disclosure can include a backplane device for exchanging audio information, video information, or other data among multiple audio, video, and/or data (AVD) processing or storage hardware modules. The backplane device includes a group of AVD module slots, and each of the module slots can receive an AVD processing hardware module, an AVD storage hardware module, or other signal processing hardware module. The backplane device includes a serial bus communication loop to couple each of the AVD module slots. The serial bus communication loop is maintained even when an AVD module slot of the backplane device is unoccupied by a hardware module. In an example, multiple backplane devices according to the present disclosure can be daisy-chained together, and packetized information can be exchanged among modules in any of the multiple backplane devices using the communication loop.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: November 19, 2019
    Assignee: TV One Limited
    Inventor: Richard Mallett
  • Patent number: 10481801
    Abstract: Various systems and methods are provided for optimizing Storage Quality of Service (SQoS) by dynamically determining and managing queue depth and system capacity in a computer storage system. In one embodiment, this functionality includes determining a queue depth value for a given epoch, and then advertising that queue depth value to one or more applications. Upon receiving a number of I/O operations that does not exceed the advertised queue depth, the storage tier processes those I/O operations. The system then evaluates the system capacity in light of the current queue depth value and other variables, such as the observed (or “seen”) latency, to determine whether the optimal queue depth value has been reached. Until the optimal queue depth value has been reached, the process outlined above is repeatedly iteratively (with dynamically increasing queue depth values) in each ensuing epoch until the optimal queue depth value is determined.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 19, 2019
    Assignee: Veritas Technologies LLC
    Inventors: Shreenivas N. Baitule, Sudhakar Paulzagade
  • Patent number: 10474622
    Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a transmitting device includes receiving a datagram to be transmitted from the transmitting device to a receiving device, determining whether a first serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, determining whether a second serial bus coupling the transmitting device to the receiving device is available to transmit the datagram, transmitting the datagram over the first serial bus when the first serial bus is available, and transmitting the datagram over the second serial bus when the second serial bus is available and when the first serial bus is unavailable. The datagram is associated with a latency budget. The first or second serial bus may be available to transmit the datagram when active and likely to transmit the datagram within a time limit defined by the latency budget.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: November 12, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Dominic Wietfeldt, Lalan Jee Mishra
  • Patent number: 10467024
    Abstract: A bus arrangement includes a coordinator that has a non-volatile memory; a first node that has a first serial number; a second node that has a second serial number; and a bus. The bus includes a first signal line, which couples the first node and the coordinator; a second signal line, which connects the second node to the first node; and at least one bus line, which connects the coordinator to the first and the second nodes. The coordinator is configured such that, in a configuration phase, it establishes a connection to the first node, queries the first serial number, and stores the first serial number in the non-volatile memory, and establishes a connection to the second node, queries the second serial number, and stores the second serial number in the non-volatile memory.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: November 5, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Matthias Hansing, Franz Heller, Peter Thiessmeier
  • Patent number: 10459854
    Abstract: A memory controller according to example embodiments of the inventive concept includes a system bus, a first direct memory access (DMA) engine configured to write data in a buffer memory through the system bus, a snooper configured to output notification information indicating whether the data is stored in the buffer memory by snooping around the system bus, and a second direct memory access (DMA) engine configured to transmit the data written in the buffer memory to a host in response to the notification information from the snooper.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JunBum Park
  • Patent number: 10452353
    Abstract: A work machine includes at least one input device configured to generate input information. A controller is coupled to the input device(s) and is configured to store the input information in a buffer. The controller is configured to detect a trigger and responsively save at least a portion of contents of the buffer to memory. A wireless communication module is coupled to the controller and is configured to transmit an external capture signal when the controller detects the trigger.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 22, 2019
    Assignee: Deere & Company
    Inventor: Eric R. Anderson
  • Patent number: 10452569
    Abstract: Systems and methods for designing a virtual platform based on user inputs. The system includes a memory that stores instructions for executing processes for designing a virtual platform based on user inputs. The system also includes a processor configured to execute the instructions. The instructions cause the processor to: receive, via an input device, a plurality of user inputs; generate the virtual platform, wherein successful inputs of the virtual platform are based on the plurality of user inputs; and store the virtual platform on a storage device such that a user may utilize the virtual platform on a computing device.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: October 22, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Robert Wesley Murrish
  • Patent number: 10447298
    Abstract: An integrated circuit includes first and second double data rate (DDR) shift registers. A multiplexor outputs a serialized data burst by selecting between a first output stream of the first DDR shift register and a second output stream of the second DDR shift register based upon a received selector signal. The selector signal is derived from clock doubling circuitry that provides a frequency that is twice a frequency of a first clock driving the first DDR shift register.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: October 15, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Stefan Dietrich
  • Patent number: 10439830
    Abstract: A bus arrangement includes: a coordinator; a first subscriber; a second subscriber; and a bus. The bus includes: a first signal line coupling the first subscriber and the coordinator; a second signal line connecting the second subscriber to the first subscriber; and at least one bus line connecting the coordinator to the first subscriber and the second subscriber. The coordinator is configured to send a message via the at least one bus line to the second subscriber with a command to activate the first subscriber via the second signal line. The first subscriber includes a first current sensor and the second subscriber includes a switchable current source. The second signal line couples the first current sensor with the switchable current source.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 8, 2019
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Matthias Hansing, Franz Heller
  • Patent number: 10437316
    Abstract: On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: October 8, 2019
    Assignee: ADVANCED PROCESSOR ARCHITECTURES, LLC
    Inventors: Louis Edmund Chall, John Bradley Serson, Philip Arnold Roberts, Cecil Eugene Hutchins
  • Patent number: 10430203
    Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: October 1, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Robert Michael Johnson, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Asif Khan, Nafea Bshara, Anthony Nicholas Liguori
  • Patent number: 10430118
    Abstract: A virtualized peripheral driver and filter are installed at a kernel level of an Operating System (OS) on a host device. A new peripheral driver is installed on the host device and added to the peripheral device stack within the OS. Events generated from the user level of the OS are pushed through the stack for processing by a newly attached peripheral of the host device using the new peripheral driver. Events produced from the kernel for the peripheral are trapped by the filter when passing up through the stack to the user level of the OS and provided to the virtualized peripheral driver. The virtualized peripheral driver repackages, translates, and formats the events produced from the kernel as OS events expected by the OS for processing and the repacked, translated, and formatted events are processed by the OS.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: October 1, 2019
    Assignee: NCR Corporation
    Inventors: Nicholas Caine, Andrew J. Wurfel
  • Patent number: 10423553
    Abstract: A system-on-chip (SoC) may include a master, a slave, and an asynchronous interface having a first first-in first-out (FIFO) memory connected to the master and the slave. A write operation of the FIFO memory is controlled based upon a comparison of a write pointer and an expected write pointer of the FIFO memory, and a read operation of the FIFO memory is controlled based upon a comparison of a read pointer and an expected read pointer of the FIFO.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: September 24, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Jin Kim, Nak-Hee Seong, Hee-Seong Lee
  • Patent number: 10423563
    Abstract: Embodiments for a memory access broker system with application-controlled early write acknowledgment support. A memory access broker may be selectively enabled to facilitate early write acknowledgement (EWACK) operations and notification of failed EWACK write requests to one or more issuing applications such that the failed EWACK write requests are logged by the memory access broker for inspection by the one or more issuing applications.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Konstantinos Katrinis, Andrea Reale, Dimitrios Syrivelis
  • Patent number: 10417148
    Abstract: A bus traffic control apparatus includes a sizing block, a traffic request controller and a bus master engine. The sizing block is configured to determine a data transmitting size of a bus master based on bus traffic information. The traffic request controller is configured to control transmission of data from the bus master based on the data, a destination of the data, the data transmitting size. The bus master engine is configured to transmit the data to the destination in the data transmitting size based on the data, the destination of the data, the data transmitting size and a request received from the traffic request controller.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Chul Song, Yong Kim, Seong-Wook Cho