Abstract: Techniques regarding routing qubit data are provided. For example, one or more embodiments described herein can comprise a computer-implemented method for training a quantum controller fast path interface that can control the qubit data routing. The computer-implemented method can comprise training, by a system operatively coupled to a processor, the quantum controller fast path interface for routing qubit data bits between a quantum controller and conditional engine by adjusting a delay value such that a mesochronous clock domain is characterized by a direct register-to-register transfer pattern.

Abstract: An energy-aware system is provided. The system includes an energy harvester adapted to supply harvested energy as an output for storage at an energy storage; and a scheduler, the scheduler being made up of, at least in part, hardware of the energy-aware system, the scheduler operable to schedule execution of operations performed by the energy-aware system, wherein the scheduler is configured to: determine if a current voltage level at the energy storage is higher than a start voltage level; and cause initiation of execution of at least a portion one of the operations when the start voltage of the one of the operations levels is lower than or equal to the current voltage level.

Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

Abstract: A system on chip (SOC) system includes functional modules, including a first and second functional module. The first and second functional module are configured to send, to an aggregation module and in a standardized message format, first and second status information associated with the first and second functional module according to a first and second set of one or more reporting rules, respectively. The aggregation module aggregates the first status information in the standardized message format and the second status information in the standardized message format and insert a timestamp to obtain a timestamped and aggregated message stream. The timestamped and aggregated message stream is stored and enables a visualization system to analyze the first functional module and the second functional module.

Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.

Abstract: A method for online reconfiguration of a node in a process control system including components. Each component is a separate executable running in a separate operating system process as provided by a real time operating system of the node. A method is performed by a node manager of the node to be reconfigured. The method includes triggering, based on new configuration data and whilst running the at least one of the components to be reconfigured, creation of a new configuration entity for each of the at least one of the components to be reconfigured, the creating involving implementing, by each new configuration entity, a part of the reconfiguration corresponding to its component to be reconfigured. The method includes triggering synchronization of runtime data in each new configuration entity with runtime data of its corresponding existing configuration entity. The method includes triggering replacement of the existing configuration entity with its new configuration entity and thereby reconfiguring the node.

Abstract: Methods and systems for detecting and responding to erroneous application configurations are presented. In one embodiment, a method is provided that includes receiving a configuration for an application and receiving execution metrics for the application. The configuration and the execution metrics may be compared to a knowledge base of reference configurations and reference execution metrics and a particular reference configuration may be identified from the knowledge base that corresponds to the configuration. The particular reference configuration may represent an erroneous configuration of the application that needs to be corrected. A configuration correction may then be identified based on the particular reference configuration.

Abstract: Automatic-switching and deployment of software (SW)- or firmware (FW)-based USB4 connection managers (CMs) and associated methods, apparatus, software and firmware. A handshake is defined between BIOS and an operating system (OS) to discover supported CM capability and dynamically switch from a FW CM to a SW CM and visa verse if there is a mismatch. In addition, a mechanism is defined to deploy the correct FW or SW CM driver based on class code, 2-part or 4-part ID. Support for continued USB4 operation during an OS upgrade or downgrade is provided, while ensuring that the best possible CM solution is used based on the advertised platform and OS capability. USB4 controllers support a pass-through mode under which the host controller FW redirects control packets sent between an SW CM and a USB4 fabric, and a FW CM mode under which control packets are communicated between the host controller FW and the USB4 fabric to configure USB4 peripheral devices and/or USB4 hubs in the USB4 fabric.

Abstract: Recommending configuration changes may include: receiving a decision tree comprising levels of nodes, wherein the decision tree includes leaf nodes each representing a different one of a plurality of hardware configurations, wherein a first leaf represents a first hardware configuration and the first leaf node is associated with a set of I/O workload features denoting a I/O workload of a first system having the first hardware configuration, wherein the set of I/O workload features is associated with an action from the first leaf node to a second leaf node, wherein the second leaf node represents a second hardware configuration and the action represents a hardware configuration change made to transition from the first to the second hardware configuration; and performing processing that determines, using the decision tree, a recommendation for a hardware configuration change for a second system having the first hardware configuration represented by the first leaf node.

Abstract: A technique manages input/output(I/O)-critical tasks and background tasks within a computer device. The technique involves identifying tasks on the computer device as I/O-critical tasks and background tasks, accessing a ready task list that indicates any ready I/O-critical tasks and any ready background tasks, and based on the accessed ready task list, performing the tasks on the computer device. Such a technique enables the computer device to make better decisions that reduce I/O latencies while still efficiently utilizing central processing unit (CPU) cycles.

Abstract: A data processor capable of suppressing variation in latency during a bus access is provided. The data processor according to one embodiment includes a ring bus through which a plurality of relay circuits, being coupled to a plurality of bus masters and a plurality of slaves, are coupled in the shape of a ring. Each of the relay circuits includes: an arbitration circuit which arbitrates an adjacent request packet of an adjacent relay circuit and a bus request packet of a nearest bus master with use of priority of these request packets, and outputs the request packet after arbitration to a next relay circuit; and a priority adjustment circuit which adjusts priority of the bus request packet according to the number of relay circuits through which the bus request packet passes before reaching its destination.

Abstract: A control system is for controlling safety-critical processes, non-safety-critical processes, and/or installation components. The control system includes: at least one control unit configured to control non-safety-critical processes and/or non-safety-critical installation components, at least one safety control unit for controlling safety-critical processes and/or safety-critical installation components, and at least one input/output unit connected to the first control unit via an internal input/output bus. The control system is configured to act as communication master or as communication minion or as both in a pool having other devices that is connected via field bus, and to that end, the control system includes a master communication coupler and a minion communication coupler. The control system is modularly configurable. At least the safety control unit includes respective subunits with master functionality and subunits with minion functionalities.

Abstract: A parallel processing apparatus includes: a first node including a storage unit that stores a program, the first node being activated when the program loaded from the storage unit is executed; a second node activated when the program loaded from the storage unit of the first node is executed; and a control unit configured to execute a setting process for setting a state where the program may be loaded to each of the first node and the second node, wherein the control unit starts the setting process on the second node after a predetermined time elapses since start of the setting process on the first node, and wherein the predetermined time is a time at which an activation completion timing of the first node is aligned with a completion timing of the setting process on the second node.

Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: Systems and devices can include an upstream port, a downstream port, and a multilane link connecting the upstream port to the downstream port, the multilane link comprising a first link width. The upstream port or the downstream port can be configured to determine that the downstream port is to operate using a second link width, the second link width less than the first link width; transmit to the upstream port an indication of a last data block for the first link width across one or more lanes of the multilane link; cause a first set lanes to enter an idle state; and transmit data on a second set of lanes, the second set of lanes defining the second link width.

Abstract: Some examples described herein relate to a boot image file. In an example, a design system includes a processor and a memory, storing instruction code, coupled to the processor. The processor is configured to execute the instruction code to compile an application to generate a boot image file. The boot image file is capable of being loaded onto and executed by a programmable device that comprises data processing engines (DPEs). The boot image file has a format comprising a platform loader and manager (PLM) and partitions. The PLM comprises code capable of being executed by a controller of the programmable device to load the partitions onto the programmable device. Each of the partitions comprises a bitstream, executable code, data, or a combination thereof. The partitions collectively include a single global partition that comprises DPE partitions that are capable of being loaded onto one or more of the DPEs.

Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

Abstract: This disclosure describes systems on a chip (SOCs) that prevent side channel attacks on encryption and decryption engines of an electronic device. The SoCs of this disclosure concurrently operate key-diverse encryption and decryption datapaths to obfuscate the power trace signature exhibited by the device that includes the SoC. An example SoC includes an encryption engine configured to encrypt transmission (Tx) channel data using an encryption key and a decryption engine configured to decrypt encrypted received (Rx) channel data using a decryption key that is different from the encryption key. The SoC also includes a scheduler configured to establish concurrent data availability between the encryption and decryption engines and activate the encryption engine and the decryption engine to cause the encryption engine to encrypt the Tx channel data concurrently with the decryption engine decrypting the encrypted Rx channel data using the decryption key that is different from the encryption key.

Abstract: A reception device that communicates with a transmission device is provided. The reception device includes a reception circuit configured to receive a clock signal, a first data signal, and a second data signal from the transmission device, a signal synchronization circuit configured to adjust the phases of the first data signal and the second data signal, and generate a first synchronization data signal and a second synchronization data signal, a signal distribution circuit configured to adjust the phase of the clock signal and generate a first distributed clock signal and a second distributed clock signal, and adjust the phases of the first synchronization data signal and the second synchronization data signal and generate a first distributed data signal and a second distributed data signal, and an output circuit configured to process the first distributed data signal and the second distributed data signal.