Patents Examined by Raymond N Phan
  • Patent number: 10574354
    Abstract: A hybrid integrated circuit (HIC) with a high bandwidth, low-power, miniaturized, optically coupled data communication interface, the interface and an arrangement including the HIC. Active and passive components and integrated circuit (IC) chips may be mounted on an HIC substrate and collecting data. The HIC is smaller than one millimeter square and communicates data externally through a microLED (?LED) array mounted on the HIC substrate and coupled to other HIC components. Each “on” ?LED consumes less than ten microwatts (10 ?W).
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Devendra K. Sadana
  • Patent number: 10572418
    Abstract: A method for integrating a further bus subscriber into a bus system, and a bus system, having a master module and subscribers disposed in series, includes the temporally consecutive method steps: in a first method step, the further bus subscriber transmits a data packet to the master module in order to log in to the master module, in a second method step, a bus subscriber disposed between the further bus subscriber and the master module stops the data packet and checks whether the bus system has already received a release, in a third method step, the first bus subscriber forwards the data packet to the master module if the bus system has not yet received a release, or in a third, in particular an alternative, method step, if the bus system has already received a release, the bus subscriber stores the data packet and waits until the release of the bus system is revoked and after the release has been revoked, forwards the stored data packet to the master module.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: February 25, 2020
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventor: Manuel Fuchs
  • Patent number: 10572414
    Abstract: Disclosed are methods and devices, among which is a device that uses a memory map to identify whether functionality of the device should be implemented. The device may be coupled to a separate device, and, in some embodiments, the device may determine and provide a response of the device to requests from the separate device.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Harold B Noyes, Stephen P. King
  • Patent number: 10565147
    Abstract: System host (2) requests a command to local device (6), and local host (10) interprets the requested command and issues the command to local device (6). Local device (6) notifies local host (10) of an interrupt of command complete and local host (10) notifies system host (2) of the command complete. Data transfer between system host (2) and local device (6) is performed via advanced switching unit (8), and advanced switching unit (8) converts an address on local host (10) side into an address on system host (2) side and transfers PCI packets between local host (10) and system host (2).
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 18, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGMENT CO., LTD.
    Inventors: Hideaki Yamashita, Takeshi Ootsuka
  • Patent number: 10565150
    Abstract: An example peripheral device includes a module interface to receive power and data communication from a computing device. The peripheral device also includes an attachment tab to affix the peripheral device to a lower side of the computing device. The peripheral device further includes a latch to control an engagement of the attachment tab with the computing device. The peripheral device further includes a sensing circuit to detect a change in position of the latch. The peripheral device further includes a controller to, in response to detecting the latch moving from a locked position to an unlocked position, indicate a hot unplug prediction to the computing device via the module interface.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: February 18, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Chi So, Nam H Nguyen, Ted T Nguy
  • Patent number: 10565004
    Abstract: In an example, memory register interrupt based signaling and messaging may include receiving, at a control register of a receiver, a signal number from a sender, and copying, by a memory register interrupt management device of the receiver, the signal number to an associated status register of the receiver. Further, memory register interrupt based signaling and messaging may include generating, independently of the signal number from the status register, an interrupt to a central processing unit of the receiver, and triggering, based on the interrupt, an interrupt handler of the receiver to perform an action associated with the signal number.
    Type: Grant
    Filed: February 4, 2016
    Date of Patent: February 18, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Jean Tourrilhes, Mike Schlansker
  • Patent number: 10565144
    Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to operate with the memory devices having a first data width in a first mode and with the memory devices having a second data width in a second mode. The control circuit may be configured to implement two differential data strobe input/output circuits. The differential data strobe input/output circuits each may have driver and termination control inputs that are independently programmable. The differential data strobe input/output circuits may be configured to be connected in parallel when the control circuit is operating in the second mode.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: February 18, 2020
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Alejandro F. Gonzalez, Craig DeSimone, Garret Davey, Yue Yu, Roland Knaack, Scott Herrington
  • Patent number: 10558610
    Abstract: A utilizing function apparatus include at least one processor, and a memory storing instructions that, when executed by the at least one processor, causes the at least one processor to, based on an operation, set one of at least one function temporarily unable to be executed, when it is detected that the utilizing function apparatus is connected to an external device after setting the one function temporarily unable to be executed, acquire information about an area of the memory of the utilizing function apparatus, as first information, when it is detected that the connection with the external device is released, acquire the information about the area of the memory, as second information, and when the acquired first information and second information are different, set the one function back able to be executed.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: February 11, 2020
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Kentaro Okuma
  • Patent number: 10545891
    Abstract: Embodiments relate to configurable processor interrupts. An aspect includes sending, by an application to supervisor software in a computer system, a request, the request including a plurality of exception types to be handled by the application. Another aspect includes determining, by the supervisor software, a subset of the plurality of exception types for which to approve handling by the application. Yet another aspect includes sending a response from the supervisor software to the application notifying the application of the subset of exception types.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind
  • Patent number: 10545902
    Abstract: A device with a physical layer (PHY) core component, a PHY I/O component, a decoupling I/O component, and a decoupling core component, where the PHY core component is adjacent to the PHY I/O component, the PHY I/O component is adjacent to the decoupling I/O component, the decoupling I/O component is adjacent to the decoupling core component and is positioned a first distance away from the PHY core component, and the decoupling core component is adjacent to an edge of the device and is positioned a second distance away from the PHY core component.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: January 28, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Mark Moty Groissman, Alex Tetelbaum
  • Patent number: 10545873
    Abstract: Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a portion of allocated pins of a processor with switchable pins, connecting the processor to a memory interface configured to switch the switchable pins between a power mode and a signal mode, providing a metric configured to identify which of the power mode and the signal mode is most beneficial during 1 millisecond intervals, and switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: January 28, 2020
    Assignee: BOARD OF SUPERVISORS OF LOUISIANA STATE UNIVERSITY AND AGRICULTURAL AND MECHANICAL COLLEGE
    Inventors: Lu Peng, Ashok Srivastava, Shaoming Chen
  • Patent number: 10545893
    Abstract: An interrupt controller, and method of operation of such an interrupt controller, are provided. The interrupt controller has an interrupt source interface for receiving interrupts from one or more interrupt sources, and a plurality of output interfaces, where each output interface is associated with a processing device that can execute an interrupt service routine to process an interrupt request issued to that processing device. The interrupt source interface has transaction generation circuitry to generate, for each received interrupt, an original transaction to represent the interrupt and a duplicate transaction to represent the interrupt. Buffer circuitry then buffers the original transaction and the duplicate transaction for each received interrupt, and selection circuitry is provided for selecting transactions from the buffer circuitry, and for routing each selected transaction for receipt by the output interface identified by an address portion of the selected transaction.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: January 28, 2020
    Assignee: Arm Limited
    Inventors: Zheng Xu, Abdul Ghani Kanawati, Timothy Nicholas Hay
  • Patent number: 10540186
    Abstract: Disclosed are techniques regarding aspects of implementing client configurable logic within a computer system. The computer system can be a cloud infrastructure. The techniques can include providing an identifier in response to configuring client configurable logic within the computer system.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: January 21, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Robert Michael Johnson, Islam Mohamed Hatem Abdulfattah Mohamed Atta, Asif Khan, Nafea Bshara, Anthony Nicholas Liguori
  • Patent number: 10534707
    Abstract: The present disclosure provides a technique of suppressing competition of processes in a semiconductor device employing a multilayer bus configuration. A semiconductor device employing a multilayer bus configuration includes a control device controlling an access from each of bus maters to each memory, and a storage device for storing a corresponding relation between identification information identifying a storage region included in each memory and a group to which the storage region belongs.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 14, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Yamaguchi
  • Patent number: 10528512
    Abstract: Systems and methods for performing asynchronous input/output (I/O) operations. An example method comprises: initializing a list of sockets that are ready for performing I/O operations; traversing the list of sockets, wherein a traversal operation of the list includes, for each socket referenced by the list: performing I/O operations using the socket, updating a state flag associated with the socket to reflect a state of the socket, updating one or more observed I/O performance statistics of the socket; and responsive to detecting less than a threshold number of I/O operation errors during the traversal operation, updating the list of sockets based on updated endpoint state flags and observed I/O performance statistics.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: January 7, 2020
    Assignee: Parallels International GmbH
    Inventors: Sergey Pachkov, Nikolay Dobrovolskiy, Serguei M. Beloussov
  • Patent number: 10528517
    Abstract: Systems and methods for power conservation in a SOUNDWIRE audio bus provide a pulse density modulated (PDM) audio stream at an audio source to an encoder. The encoder has a plurality of encoding states corresponding to bit patterns. The encoder compares bits of the audio stream to available bit patterns and selects an encoding state. The audio source sends the encoding state to an audio sink and then sends data to the audio sink based on encoding using the selected encoding state. The data is sent over a non-return to zero inverted (NRZI) audio bus. As the audio stream changes bit patterns, the encoder may select different more efficient encoding states and provide updates to the audio sink of changes in the encoding state.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Sandeep Kumar, Suman Kumar, Lior Amarilio
  • Patent number: 10528509
    Abstract: The present disclosure discloses an expansion bus device that is communicatively coupled to a plurality of input-output devices. The expansion bus device includes a plurality of input-output slots, via which the plurality of input-output devices are coupled to the expansion bus device. The expansion bus device also includes a retimer switch communicatively connected to each of the plurality of input-output slots. The retimer switch supports switching between the plurality of input-output slots.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: January 7, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Glenn H. Lupton, Michael L. Sabotta, Brian T. Purcell, Patrick Raymond
  • Patent number: 10528393
    Abstract: A method for operating a data storage device includes determining a first weight based on the sum of data sizes for commands queued in a command queue; determining a second weight by summing weights by types of the commands; and controlling an urgent command selection threshold value for selecting an urgent command existing in the command queue, based on at least one of the first weight and the second weight.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: January 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Jeen Park
  • Patent number: 10521374
    Abstract: Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: December 31, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiromichi Yamada, Akihiro Yamate, Yoichi Yuyama
  • Patent number: 10521376
    Abstract: An apparatus may include a baseboard management controller (BMC) configured to monitor one or more statuses of a storage array enclosure of the BMC. The BMC may further communicate with a host device of a PCIe network topology via a PCIe port of the BMC including performing a direct memory access (DMA) write to store status information of the enclosure to a memory of the host device via the PCIe network topology and performing a DMA read to retrieve control information from the memory of the host device via the PCIe network topology. In addition, the BMC may control one or more devices of the storage array enclosure based on the retrieved control information.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 31, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sumanranjan Mitra, Ajit Patil, Sivaprakash Rajaram