Abstract: A cable assembly for providing a data acquisition system with data messages passing on a fieldbus of rolling stock, said cable assembly comprising a data listener adapted to listen in on said data messages passing on said fieldbus; a data transmitter adapted to transmit said data messages to said data acquisition system; and an isolation module adapted to electrically isolate said data transmitter from said data listener and from said fieldbus, thereby electrically isolating said data acquisition system from said fieldbus such that said data acquisition system is limited by said isolation module to only listening in on said data messages passing on said fieldbus.

Abstract: Systems and methods for network port monitoring using low energy wireless communications are provided. In one embodiment, a device comprises: at least one port module, the at least one port module comprising one or more connector ports each configured to receive a connector of a network data cable; and a port state sensor that includes a port sensing circuit coupled to a sensor controller, wherein the port sensing circuit is configured to sense a port state for the one or more connector ports; wherein the sensor controller is configured to input the port state from the port sensing circuit, wherein in response to detecting a change in the port state from the port sensing circuit, the sensor controller wirelessly transmits port state information to a port state monitor.

Abstract: An information handling system includes a synchronizer and a module identifier. The module identifier identifies a module identification event for a module attached to the information handling system; in response to identifying the module identification event: obtains a module identifier from the module, and makes a determination that the module identifier indicates that the module is a synchronization type of module, and initiates, based on the determination, time synchronization for the information handling system with a second information handling system using the module and the synchronizer.

Abstract: An apparatus may include a basic input/output system (BIOS) coupled to a controller. A communication port may be coupled to the controller. The controller may determine that the communication port has entered a locked state, send a first signal to the communication port to power off a bus associated with the communication port for a threshold period of time, and send a second signal to the communication port to power on the bus associated with the communication port in response to expiration of the threshold period of time.

Abstract: This embodiment relates to a transmitter and the like that prevent an increase of the number of cables of an external interface even when the types of signals to be transmitted increase. The transmitter includes a latch circuit, an encoder, a serializer, and a selector. The latch circuit keeps a level of each of a plurality of signals at the timing specified by a sampling clock, and then, outputs the plurality of signals as a parallel data signal. The encoder generates an encoded parallel data signal based on the parallel data signal from the latch circuit. The serializer generates a serial data signal based on the encoded parallel data signal from the encoder. The sampling clock has a frequency higher than a transmission rate of the fastest signal of the plurality of signals.

Abstract: Described is a two-phase spinlock that controls access to a resource from a plurality of threads. The two-phase spinlock receives requests from threads to acquire the resource, places the threads in a first queue associated with a first phase of the two-phase spinlock, determines whether at least one of a predetermined number of slots in a second phase of the two-phase spinlock is available and when the slots are unavailable, processes an interrupt served by a select one of the threads based on a number of attempts by the selected thread to enter the second phase.

Abstract: A VR headset and a method for controlling a VR headset are provided. The VR headset comprises a wakeup/sleep control circuit, at least one pressure sensor and at least one distance sensor, the pressure sensor and the distance sensor each being electrically connected with the wakeup/sleep control circuit, wherein the pressure sensor is provided at an upper frame and/or a lower frame of the VR headset, and the distance sensor is provided at an inner side of the VR headset, the inner side of the VR headset referring to a side of the VR headset that is adjacent to a face of a user wearing the VR headset. The VR headset provides a hardware basis for an automatic wakeup/sleep control of the VR headset.

Abstract: Systems and methods described in this disclosure relate, generally, to analyzing electronic circuitry, and more specifically, to analyzing efficiency of clock gating in electronic circuitry. Analysis may include identifying wasted propagation of clock signals by clock gates and/or for a circuitry as a whole. In some embodiments, modified gating logic may be determined that improves clock gating efficiency, for example, by eliminating at least some wasted propagation of clock signals.

Abstract: Systems, methods, and devices are provided for migrating field device data signals from a first control system to a second control system using an interface card. An interface card can be configured to couple to a first and second terminal block cable assembly, respectively associated with a first and second control system. The interface card and system herein can maintain a field device data channel assignment configuration when migrating control and data I/O of the field device from the first control system to the second control system.

Abstract: A memory module may include: a plurality of stacked memory chips; a memory controller; and an interposer connected between the plurality of memory chips and the memory controller.

Abstract: A NUMA-aware storage system including a first processing subsystem coupled to a first memory subsystem, and a second processing subsystem coupled to a second memory subsystem. A first NTB subsystem connected to the first processing subsystem presents itself as a first storage device, identifies first data transfer operations directed to the first memory subsystem and, in response, claims those first data transfer operations and provides them directly to the first processing subsystem. A second NTB subsystem connected to the second processing subsystem presents itself as a second storage device, identifies second data transfer operations directed to the second memory subsystem and, in response, claims those second data transfer operations and provides them directly to the second processing subsystem. A storage controller system receives a command from either the first or second processing subsystem via the first or second NTB subsystem and, in response, transmits that command to a storage system.

Abstract: An integrated circuit may include a printed circuit board and multiple processor sockets on the printed circuit board. Each of the multiple processor sockets is operable to receive a microprocessor and a programmable device. When a microprocessor is placed in a processor socket, that microprocessor may communicate with memory dual in-line memory modules (DIMMs). When a programmable device is placed in a processor socket, that programmable device may first be configured using a configuration DIMM and may then communicate with memory DIMMs during normal operation. The configuration DIMM may include multiple options for configuring the programmable device and may also provide additional management functions specifically tailored to the programmable device.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: Provided is a graphics processing unit and an operation method thereof. The graphics processing unit includes a plurality of cores in which a delay time between an input and an output decreases according to an increase of a temperature, a temperature monitoring and sorting circuit configured to monitor a temperature of each of the plurality of cores, and a controller configured to control a clock frequency and a power supply of the plurality of cores based on a drivable clock frequency of a core having the lowest temperature among temperatures of each of the plurality of monitored cores.

Abstract: An apparatus for managing input/output (I/O) data may include a streaming I/O controller to receive data from a load/store domain component and output the data as first streaming data of a first data type comprising a first data movement type and first data format type. The apparatus may also include at least one accelerator coupled to the streaming I/O controller to receive the first streaming data, transform the first streaming data to second streaming data having a second data type different than the first data type, and output the second streaming data. In addition, the apparatus may include a streaming interconnect to conduct the second data to a peer device configured to receive data of the second data type.

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

Abstract: Provided a device that performs at least one of an input and an output, a device power supply control unit that controls power supply to the device, and a device power supply control instruction unit that instructs the device power supply control unit to stop power supply to the device based on an instruction from an operation unit arranged in the apparatus, wherein stopping power supply to the device makes it possible to set the device that is fixedly connected in the apparatus to a pseudo removed state.

Abstract: According to one embodiment, the first processing unit receives a first clock and outputs, at its first output node, data obtained by first processing of data at an input node. The second processing unit receives a first clock and outputs, at its second output node, data obtained by the first processing of the data at the input node. The third processing receives a second clock, outputs, from its third output nodes, data obtained by the first processing of the data at the input node, and outputs, from its fourth output nodes, data obtained by the first processing of the data at the input node. The determination unit outputs a first signal based on data at the fifth to eighth nodes respectively coupled to the first to fourth output nodes.

Abstract: A storage device is provided. The storage device includes a field programmable gate array board connected to a first port of the storage device; and a storage controller including a first interface circuit and a second interface circuit. The first interface circuit is connected to the FPGA board, the second interface circuit is connected to a second port of the storage device, at least one port from among the first port and the second port being configured to connect to an external storage device, and the FPGA board is configured to provide a path for transferring data in a peer-to-peer manner between the storage controller and the external storage device without intervention of a host.

Abstract: A device may include a memory storing instructions and a processor configured to execute the instructions to receive, from a configuration client device, a request to register a resource; and identify a domain object associated with the resource, wherein the domain object corresponds to a logical entity representing a device or port, or corresponds to a logical entity controlling another resource included in another domain object. The processor may be further configured to select a domain object handler for the identified domain object; register the identified domain object with the selected domain object handler; and use the selected domain object handler to process messages associated with the registered domain object.