Abstract: A power supply architecture for USB Type-C controllers is described herein. In an example embodiment, an integrated circuit (IC) controller comprises a VCONN pin, a power rail coupled to internal circuits of the IC controller, and a VCONN switch coupled between the VCONN pin and the power rail. The VCONN switch comprises: a drain-extended n-type field effect transistor (DENFET) coupled between the VCONN pin and the power rail; a pump switch coupled to a gate of the DENFET; a resistor coupled between the VCONN pin and the gate of the DENFET; and a diode clamp coupled between the gate of the DENFET and ground.

Abstract: A memory module includes arrays of memory devices each having a data bus coupled to the data bus of a host memory channel by means of a switching tree. The switching tree is a tree of multiplexers that are controlled to couple the data lines of a single array to the data bus. In some embodiments, a first portion of the chip enable (CE) lines of a memory module are used to enable arrays of memory devices and a second portion are used to control the switching tree. The first portion may control a switching tree coupling the first portion to the enable inputs of the arrays.

Abstract: Methods, systems, and devices for a latency indication in a memory system or sub-system are described. An interface controller of a memory system may transmit an indication of a time delay (e.g., a wait signal) to a host in response to receiving an access command from the host. The interface controller may transmit such an indication when a latency associated with performing the access command is likely to be greater than a latency anticipated by the host. The interface controller may determine a time delay based on a status of buffer or a status of memory device, or both. The interface controller may use a pin designated and configured to transmit a command or control information to the host when transmitting a signal including an indication of a time delay. The interface controller may use a quantity, duration, or pattern of pulses to indicate a duration of a time delay.

Abstract: In one example, an apparatus comprises: a first local memory, a computation engine configured to generate local data and to store the local data at the first local memory, and a controller. The apparatus is coupled with a host processor and a second device via an interconnect, the second device comprising a second local memory, the host processor hosting an application. The controller is configured to: receive, from the second device, a first message indicating that first data is stored in the second local memory; based on the first message: fetch the first data from the second local memory via the interconnect; control the computation engine to perform a computation operation on the first data to generate second data to support the application hosted by the host processor; and transmit, to the second device, a second message indicating that the second data is stored in the first local memory.

Abstract: Expanded function datagrams in a system power management interface (SPMI) system allow a slave to use an expanded function datagram to address a larger number of masters (e.g., more than four) associated with the SPMI system. Furthermore, addressing may allow for a datagram to be broadcast to multiple masters concurrently. Still further, by signaling that the master addressing is other than the standard SPMI format, the nature of the address and payload of a datagram may be varied to handle larger volumes of data than the SPMI standard normally allows.

Abstract: A thread executing a task at a node in a multi-socket computing system may access a first data structure to obtain a first calibration dataset for the node. The first thread may generate a timestamp based on the first calibration dataset and a first quantity of time measured by a clock at the first node. The real-time duration of the task may be determined based on the timestamp. The first thread may recalibrate the first clock by at least generating, based on the first quantity of time measured by the clock and a second quantity of time measured by a wall clock of an operating system of the multi-socket computing system, a second calibration dataset. The first thread may update the first data structure to include the second calibration dataset while a second thread accesses a second data structure to obtain calibration data.

Abstract: Systems and methods for managing battery runtime and performance based upon presence detection are described. In some embodiments, a method may include: receiving a first amount of energy from a power source directed to supporting operation of an Information Handling System (IHS); receiving a second amount of energy from the power source directed to charging a battery of the IHS; determining a user's presence state with respect to the IHS; and modifying the first and second amounts in response to the presence state.

Abstract: A method is implemented by a control terminal communicable with a computer, and includes: receiving a modification request, obtaining a configuration path that contains a target option name of a target option to be modified and a target page name of a target page; obtaining a current page name of a current page presented in a current setup screen of BIOS of the computer; transmitting a control instruction to the computer so as to enable the computer to switch contents presented in the current setup screen from the current page to the target page, and to change option selection from a current option to the target option; and transmitting a modification instruction to the computer so as to enable the computer to modify the target option to have a target configuration value.

Abstract: A circuit for an I/O module, the circuit having a communication unit for receiving process data, which is connectable to a bus for communication purposes, a microcontroller which is connected to the communication unit, a load, a digital/analog converter, which includes a current output driver for outputting an output current to the load, and a first DC/DC converter. The microcontroller is connected to the digital/analog converter via a digital interface and is configured to set the output current of the digital/analog converter via the digital interface based on the received process data. The microcontroller is configured to output a control signal to a first DC/DC converter via the control interface for setting the first supply voltage based on the output current and the digital voltage value.

Abstract: A communication device for a vehicle includes: a memory; and a processor that is coupled to the memory, the processor being configured to: generate a first address for a time at which a first control device, which carries out control of a vehicle, communicates with a second control device, carry out communication with the second control device via the first address, and receive, from the second control device, information that specifies the first control device, and on the basis of the information that is received, set, in place of the first address, a second address that corresponds to an instrument that the first control device controls.

Abstract: A memory controller controls a data storage device including a nonvolatile memory in which a recovery code is stored. The memory controller includes: a mode converter for determining an operation mode of the data storage device as a normal mode or a sleep mode, according to power sensing information representing a power consumption of the data storage device, a recovery code storage including a nonvolatile memory, in which a recovery code for a recovery operation is stored, and a code executer for performing the recovery operation by executing the recovery code. The mode converter stores a recovery code address indicating a position of the nonvolatile memory at which the recovery code is stored.

Abstract: An information handling system couples a solid state drive assembly having plural solid state drives to a motherboard with a single M.2 connector coupled to the motherboard by interfacing the plural solid state drives with an adapter circuit board having an M.2 interface defined at one end to insert into the motherboard connector and having plural M.2 connectors to interface with the plural solid state drives in a desired configuration, such as a stacked vertical configuration that more efficiently uses motherboard footprint to include persistent memory.

Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method of operating compute units is presented that includes forming compute units among a plurality of physical computing components coupled over a Peripheral Component Interconnect Express (PCIe) fabric configured to communicatively couple the plurality of physical computing components and isolate the compute unit using logical partitioning within the PCIe fabric. The method also includes initiating a software component deployed to at least associated CPUs within the compute units, reporting telemetry to the management processor related to operation of the compute unit, and emulating operation of at least one among an Ethernet and InfiniBand interface to an operating system of the associated CPU for transfer of communications comprising at least the telemetry to the management processor over the PCIe fabric.

Abstract: A power sequence monitoring system is disclosed, and comprises: a microprocessor and a control module. The microprocessor comprises a first conversion unit and a second conversion unit. The first conversion unit is used for converting a power-on signal received from a power management chip to a first digital signal, and the second conversion unit is adopted for converting a power-off signal received form the power management chip to a second digital signal. After receiving the first digital signal and the second digital signal from the microprocessor, and the control module outputs a plurality of power monitoring data to an electronic device, such that a user easily knows the power signal state of the host computer by the system of the present invention.

Abstract: An embodiment of a semiconductor package apparatus may include technology to store cache line spare information in a first memory, detect a first power state change for the first memory, and save the cache line spare information to a second memory based on the detected first power state change. Other embodiments are disclosed and claimed.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: Power regulation in an integrated memory assembly having control semiconductor dies and memory semiconductor is disclosed herein. A master control die regulates power usage by the integrated memory assembly. Each control die reports information about its expected power usage to the master control die. The master control die determines a plan that meets a power criterion for the integrated memory assembly. The plan may maximize the power usage in each time period, while staying within a power budget. The plan can include selecting which of the memory dies perform a memory operation (or phase of a memory operation) during a given time period. The master control die may send a die scheduling plan to each of the other control dies. Each die scheduling plan indicates when memory operations and/or phases of memory operations are to be performed.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include ports to receive requests from a host and to send requests to a second storage device. The SSD may include flash storage for data. An SSD controller may process the requests received from the host and generate the requests sent to the second storage device. The SSD may act as a cache for the second storage device.