Abstract: Techniques to control a storage system involve: determining whether available power capable of being supplied by a supplying apparatus of the storage system is less than power required by the storage system; and in response to a determination that the available power is less than the power required by the storage system, adjusting an operation parameter of the storage system based on the available power so as to match the power required by the storage system with the available power. In this way, the performance of the storage system can be at a higher level while the performance of the storage system can remain stable in a case where power of a processor is limited.

Abstract: The product detection system includes a computing device, at least one power detection instrument and a product detection device. The product detection device includes a processing unit, plural USB-C transmission ports and plural detection connection ports. A product detection method includes following steps. Firstly, at least one USB-C under-test product is connected with the plural USB-C transmission ports, and the at least one power detection instrument is connected with the plural detection connection ports. Then, the USB-C transmission port is set as a first role or a second role. Then, the USB-C transmission port corresponding to the first role is cyclically operated at plural designated voltages under control of the processing unit, and the processing unit issues an output voltage to the USB-C transmission port corresponding to the second role. Then, an operation status of the USB-C under-test product is detected.

Abstract: Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

Abstract: A method for establishing an application prediction model, a storage medium, and a terminal are provided. The method includes the following. In response to an operation switching an application previously running in the foreground to a first application currently running, a first preorder usage sequence of the first application currently running is collected as sample usage information. Applications launched within a time-window are monitored, and a preset number of applications launched first in the applications launched within the time-window are set as sample labels for the sample usage information. A predetermined machine learning model is trained based on the sample usage information and the sample labels for the sample usage information, to obtain the application prediction model.

Abstract: Systems and methods disclosed herein provide a novel solution for PCIe port bifurcation. Unlike conventional client systems, which rely on resistors, jumpers or DIP switches, the disclosed systems and methods enable PCIe ports to be configured in accordance with a plurality of user-selectable PCIe bifurcation settings provided within a boot setup menu. When an “Auto” setting is selected in the boot setup menu, the disclosed systems and methods enable PCIe ports to be: (a) configured in accordance with the bifurcation requirements of the PCIe adapter card(s) connected to the PCIe ports, and (b) automatically reconfigured when bifurcation requirements change. Unlike conventional server systems, which require the user to enter BIOS setup and manually change the PCIe bifurcation settings provided in the BIOS setup menu, the systems and methods disclosed herein enable PCIe ports to be automatically reconfigured, when bifurcation requirements change, without user intervention.

Abstract: The present technology relates to an electronic device. A data transmission circuit that receives data from an outside and transmits the received data, wherein the data transmission circuit includes a storage configured of a plurality of stages that stores the data, and a reset control circuit configured to generate a signal based on the data.

Abstract: A method is provided to access a data storage memory that stores data signals in a plurality of indexed memory locations. An access control circuit receives a memory access request signals from a processing circuit. The method includes replicating the respective memory access request signals to provide for each a respective replicated memory access request signal, accessing indexed internal memory locations to retrieve a first data signal retrieved as a function of the respective memory access request signal and a second data signal retrieved as a function of the respective replicated memory access request signal, and checking for identity the first data signal and the at least one second data signal. The access control circuit transmits to the processing circuit a data signal or an integrity error flag signal as a result of the identity check.

Abstract: A communications interface for interfacing between a host system and a state machine includes an event slot, the event slot comprising a plurality of registers including: a write register for writing by the host system, and a read register for reading by the host system, wherein the event slot is addressed from the host system by a single address location permitting the host system to write data to the write register and/or read data from the read register; and wherein the write register and the read register are individually addressable by the state machine.

Abstract: A system and method of scheduling tasks, comprising receiving activity and performance data from registers or storage locations maintained by hardware and an operating system; storing calibration coefficients associated with the activity and performance data; computing an energy dissipation rate based on at least the activity and performance data; and scheduling tasks under the operating system based on the computed energy dissipation rate.

Abstract: A method of common controller area network (CAN) bus traffic supervision on a system having a common CAN bus, a first CAN chip and a second CAN chip, the first CAN chip and the second CAN chip are coupled together with the common CAN bus, the method includes comparing a first CAN frame received from the first CAN chip to a second CAN frame received from the second CAN chip within a CAN comparison period, and detecting a failure of at least the first CAN chip or the second CAN chip. Detecting the failure of at least the first CAN chip or the second CAN chip includes determining that the first CAN frame is not identical to the second CAN frame within the CAN comparison period.

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

Abstract: One or more aspects of the present disclosure relate to data protection techniques in response to power disruptions a power supply from a continuous power source for a storage device can be monitored. A power disruption event interrupting the power supply from the continuous power source can further be identified. In response to detecting an event, a storage system can be switched to a backup power supply, power consumption of one or more components of the storage device can be controlled based on information associated with each component and an amount of power available in the backup power supply. Further, one or more power interruption operations can be performed while the backup power supply includes sufficient power for performing the power interruption operations.

Abstract: An information handling system may include a processor, non-transitory computer readable media communicatively coupled to the processor and having stored thereon a primary operating system of the information handling system and a secondary operating system of the information handling system, and a basic input/output system communicatively coupled to the processor and having provisioned thereon a signed signature of the secondary operating system signed with a private key of a public-private key pair and a public key of the public-private key pair. The basic input/output system is configured to, responsive to a determination to boot to the secondary operating system in lieu of booting to the primary operating system of the information handling system verify the secondary operating system using the signed signature of the secondary operating system and the public key and responsive to verifying the secondary operating system, allow the information handling system to boot to the secondary operating system.

Abstract: A memory system may include: a memory device suitable for storing data; and a controller suitable for controlling the memory device. The controller may include: a power manager suitable for deciding whether to operate in a power saving mode based on current time; a phase locked loop suitable for generating a clock whose frequency is lowered depending on the deciding whether to operate in the power saving mode; and a processor suitable for operating at speed based on the clock.

Abstract: An apparatus and method for controlling an interface between a plurality of processors in an electronic device are disclosed. The electronic device may include: a first integrated circuit; a second integrated circuit; and a Peripheral Component Interconnect Express (PCIe) interface interconnecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit may be configured to identify the required latency level associated with a service provided by the electronic device, and restrict the use of at least one power mode among a plurality of power modes supported by the PCIe interface, based on the required latency level associated with the service. Additional embodiments are possible.

Abstract: A method of applying a data format in a direct memory access transfer is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a single chassis that couples the storage nodes as a cluster, each of the plurality of storage nodes having nonvolatile solid-state memory for user data storage. The method includes reading a self-describing data portion from a first memory of the nonvolatile solid-state memory and extracting a destination from the self-describing data portion. The method includes writing data, from the self-describing data portion, to a second memory of the nonvolatile solid-state memory according to the destination.

Abstract: A signal receiving circuit is provided. The signal receiving circuit includes a receiving circuit, an adjustment circuit and a boundary detection circuit. The receiving circuit is configured to receive an input signal. The adjustment circuit is configured to adjust the input signal. The boundary detection circuit is configured to detect a first signal having a first data pattern in the input signal and a second signal having a second data pattern in the input signal. The boundary detection circuit is further configured to detect a gap value between a first signal boundary of the first signal and a second signal boundary of the second signal to reflect a status of the adjustment circuit.

Abstract: Provided are a power-on processing method and apparatus of a terminal device, and a terminal device, and the method includes: detecting whether a fingerprint input operation is performed on the fingerprint device, when the operating system of the terminal device is in a non-working state; controlling the fingerprint device to collect fingerprint data corresponding to the fingerprint input operation when it is detected that the fingerprint input operation is performed on the fingerprint device; detecting whether the fingerprint input operation triggers the power button, when it is detected that the fingerprint input operation is performed on the fingerprint device; and transmitting the fingerprint data collected by the fingerprint device to the operating system for security verification, when it is detected that the fingerprint input operation triggers the power button.

Abstract: As described herein, a method performed in response to a client device undergoing an at least partial warm reset or reboot may include receiving a firmware commit request from a client device. The method may also include writing, at a first time, a firmware image associated with the client device into execution memory of volatile memory. The method may also include writing, at a second time, the firmware image associated with the client device into a memory slot of non-volatile memory.

Abstract: In an approach to storage level load balancing, the load level of a storage system is monitored, where the load level is a utilization percentage of a plurality of CPU cores in the storage system. An overload condition is detected based on the utilization percentage of one or more CPU cores exceeding a threshold, where the overload condition is caused by an overlap of one or more I/O queues from multiple host computers accessing a single CPU core. Responsive to detecting the overload condition, a new I/O queue is selected on a second CPU core, where the second CPU core has a utilization percentage less than a second threshold. A recommendation is sent to a host computer, where the recommendation is to move I/O traffic from the first CPU core to the new I/O queue on the second CPU core to rebalance the load level of the storage system.