Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include ports to receive requests from a host and to send requests to a second storage device. The SSD may include flash storage for data. An SSD controller may process the requests received from the host and generate the requests sent to the second storage device. The SSD may act as a cache for the second storage device.

Abstract: A logical device for implementing a service can be dynamically assigned to an available real device. A real device assignment request relating to a registered service program is transmitted to a real device assignment determination section (112) under the control of a registration management section (1111) of a service program management section (111). An assignment of a logic device relating to the service program to a real device is determined based on logic device information, real device interface assignment information, and real device information relating to an available real device under the control of the real device assignment determination section (112). Based on the assignment information, communication processing of a control command and data between the logic device relating to the service program and the real device to which the logic device is assigned.

Abstract: The present invention discloses an interrupt controller, including: a sampling unit adapted to receive interrupts from various interrupt sources coupled to the interrupt controller and perform sampling on the received various interrupts; and a priority arbitration unit adapted to classify the received various interrupts into a plurality of interrupt segments, where each interrupt segment includes one or more sampled interrupts, and determine, segment by segment an interrupt with the highest priority in a selected segment, until an interrupt with the highest priority among all interrupts is identified through arbitration and used as an to-be-responded-to interrupt. The present invention further discloses a processor including the interrupt controller, and a system-on-chip.

Abstract: A method for addressing a slave device in a network system comprising a master device and a plurality of slave devices. The slave devices have a common default address in an unaddressed state and the master device and the plurality of slave devices are connected in chain via a power line and a communication line, wherein each slave device is indexed by an index greater than or equal to 1, the slave device of index 1 being connected to the master device, wherein, to address the slave device of index k, k being equal to or greater than 2, the method first instructs the slave device of index k?1 to activate the power supply of the slave device of index k via the power line, and then, it sends, to the common default address on the communication line, a command to change the common default address of the slave device of index k to a unique address of index k. Therefore, at each iteration, there is only one unaddressed slave device in the network.

Abstract: Systems and method include one or more die coupled to an interposer. The interposer includes interconnection circuitry configured to electrically connect the one or more die together via the interposer. The interposer also includes translation circuitry configured to translate communications as they pass through the interposer. For instance, in the interposer, the translation circuitry translates communications, in the interposer, from a first protocol of a first die of the one or more die to a second protocol of a second die of the one or more die.

Abstract: A non-transitory computer-readable storage medium may be executable by a processor to receive a designation of a message bus producer, a set of business logic to be stored in a set of containers, a designation of a message bus consumer, and a designation of a set of message-handling functions. The non-transitory computer-readable storage medium may generate a serverless application stack, based upon the message bus producer, the set of business logic, the message bus consumer, and the set of message-handling functions. The non-transitory computer-readable storage medium may cause the serverless application stack to receive a message stream from the message bus producer as streaming data, process the message stream according to at least one function, stored in the set of containers, perform at least one message-handling function of the set of message-handling functions on the message stream, and transport the set of messages to the message bus consumer.

Abstract: A method of loading an executable image for a computing system includes identifying segments of at least one executable image available for loading into memory of the computing system. Each segment is associated with one or more configuration features for the computing system. At least a first segment of the at least one executable image to load into the memory of the computing system is determined, based on the first segment satisfying one or more conditions associated with the computing system. The first segment of the executable image is loaded into the memory of the computing system. At least a second segment of the at least one executable image is made available for memory re-allocation, based on the second segment not satisfying the one or more conditions associated with the computing system. Various additional and alternative aspects are described herein.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may configure multiple link registers, of a first semiconductor package of an information handling system (IHS), that configure an input/output (I/O) communication fabric of the first semiconductor package to route communications of multiple components of the first semiconductor package to multiple inter-processor communication link interfaces; may communicate with a second semiconductor package of the IHS via the multiple inter-processor communication link interfaces; may determine that a link utilization value of multiple link utilization values is at or above a threshold value; and may configure a link register of the multiple link registers, associated with the at least one component of the multiple components, that configures the I/O communication fabric to route communications of the at least one component of the multiple components to a second inter-processor communication link interface of the multiple inter-processor communica

Abstract: Techniques related to hosted client management comprising providing a hosted client instance over a network interface for communicatively coupling with a remote client device, the hosted client instance including a first application component for performing a first plurality of actions associated with the hosted client instance and a second application component for performing a second plurality of actions, monitoring, by the first application component, the second application component for an event associated with the second application component, determining that the event impacts the first application component based on one or more dependency tables associated with the second application component, and displaying, in a user interface of the first application component, information related to the event.

Abstract: A method for checking program execution of a microcontroller relating to a peripheral device in data communication with a microcontroller via a communication bus includes monitoring the microcontroller by an external device, identifying a failure status of the microcontroller by the external device based on the monitoring, disconnecting data communication between the peripheral device and the microcontroller by the external device, establishing a supplementary data communication between the external device and the peripheral device, and sending configuration information to the peripheral device by the external device via the supplementary data communication.

Abstract: A clock data recovery device includes a phase detector circuitry, a signal control circuitry, and interpolators. The phase detector is configured to detect a phase of an input signal, according to first clock signals, to generate first control signals, and phases of the first clock signals are different to each other. The signal control circuitry is configured to rearrange the first control signals to output as second control signals. The phase interpolators are configured to output second clock signals and alternatively adjust the phases of the second clock signals according to the second control signals to generate an output clock signal.

Abstract: An operation method of an end node including a physical (PHY) layer unit and a controller unit in a vehicle network includes: detecting, by the controller unit, a local event; in response to detecting the local event, transitioning an operation state of the controller unit from an OFF state to an ON state; transmitting, by the controller unit, to the PHY layer unit an indicator requesting to transmit a wake-up signal in accordance with the local event; and transmitting, by the PHY layer unit, the wake-up signal including an identifier of at least one end node required to be woken up by the local event.

Abstract: An apparatus such as a network switch includes a power supply device configured to control power supplied through ports such as Ethernet ports to the network devices such as wireless access portions that are part of a local network. The apparatus further includes a second power supply device with one or more switched outlets for providing direct power other devices of the local network. A controller in the apparatus may be programmed to control the power supply devices to execute to a diagnostic procedure or a reset procedure that cycles power, off and then on, to devices of the local network.

Abstract: A bus data analysis method comprises the steps of receiving an input signal, decoding the input signal according to a protocol, thereby extracting a data signal from the input signal, and analyzing the data signal extracted from the input signal statistically, thereby generating a statistically analyzed data signal. Furthermore, a bus data analysis system is described.

Abstract: A processor comprises multiple cores and power management control logic to determine (a) a preliminary frequency for each of the cores and (b) a maximum frequency, based on the preliminary frequencies. The power management control logic is also to determines a dynamic tuning frequency, based on the maximum frequency and a reduction factor. In response to the dynamic tuning frequency for a selected core being greater than the preliminary frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the dynamic tuning frequency. In response to the preliminary frequency for the selected core being greater than the dynamic tuning frequency for that core, the power management control logic is to set the core to a frequency that is at least equal to the preliminary frequency. Other embodiments are described and claimed.

Abstract: A system includes a power distribution unit and power manager circuitry. The power manager circuitry to receive a first load profile of a first information handling system, a second load profile of a second information handling system, and a third load profile of a third information handling system. The load profiles are based on power telemetry of the associated server. The power manager circuitry creates an aggregate load profile based on the first, second, and third load profiles, and determines whether the aggregate load profile exceeds a maximum load of the power distribution unit. If the aggregate load profile exceeds the maximum load of the power distribution unit, the power manager circuitry provides an optimal set of power recovery delays for a first, second, and third information handling system and also provides a power supply load limit exceeded warning message.

Abstract: A machine automation system for controlling and operating an automated machine. The system includes a controller and sensor bus including a central processing core and a multi-medium transmission intranet for implementing a dynamic burst to broadcast transmission scheme where messages are burst from nodes to the central processing core and broadcast from the central processing core to all of the nodes.

Abstract: An apparatus includes a plurality of root ports serving as roots of bus connection of a plurality of devices including boot devices from which legacy boot is executed to boot an operating system (OS). A processor included in the apparatus identifies a single boot device among the boot devices and a single root port connected to the single boot device, and allocates, as memory addresses to be used for memory mapped input and output, memory addresses with a bit width available during the legacy boot to devices connected to the identified single root port. The processor determines whether the memory addresses have been allocated to all devices connected to the single root port, and executes the legacy boot to boot the OS from the single boot device when the memory addresses have been allocated to all the devices connected to the single root port.

Abstract: Various embodiments of methods and systems for a power and performance-optimized secure image load boot flow in a specialty metering device (“SMD”) are disclosed. An exemplary method includes a CPU that transitions into an idle state, such as a WFI state, for durations of time during a boot sequence that coincide with processing by a DMA engine. That is, the CPU may “sleep” while the DMA engine processes workloads in response to instructions it received from the CPU.

Abstract: An apparatus includes a plurality of subsystems, including a first subsystem and a second subsystem. The apparatus includes a master processor to, in response to a power on of the apparatus, execute first instructions to configure the first subsystem and provide second instructions. The apparatus further includes a slave processor to, prior to the boot of the apparatus, receive the second instructions from the master processor and execute the second instructions to configure the second subsystem.