Abstract: The present invention relates to screen-printable quaternary chalcogenide compositions. The present invention also provides a process for creating an essentially pure crystalline layer of the quaternary chalcogenide on a substrate. Such coated substrates contain p-type semiconductors and are useful as the absorber layer in a solar cell.

Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.

Abstract: In order to form a high quality film without causing in-plane nonuniformity in film quality, an apparatus for forming deposited film according to an aspect of the present invention includes: a chamber; a first electrode located in the chamber; a second electrode that is located in the chamber with a predetermined spacing from the first electrode and includes a plurality of supply parts configured to supply material gases; an introduction path connected to the supply parts, through which the material gases are introduced; a heater located in the introduction path; and a cooling mechanism configured to cool the second electrode.

Abstract: A method for making a semi-conductor nanocrystals, including at least the steps of: making a stack of at least one uniaxially stressed semi-conductor thin layer and a dielectric layer, annealing the semi-conductor thin layer such that a dewetting of the semi-conductor forms, on the dielectric layer, elongated shaped semi-conductor nanocrystals oriented perpendicularly to the stress axis.

Abstract: A wafer comprising at least one emitter-up Heterojunction Bipolar Transistor (HBT) and at least one emitter-down HBT on a common InP based semiconductor wafer. Isolation and N-type implants into the device layers differentiate an emitter-down HBT from an emitter-up HBT. The method for preparing a device comprises forming identical layers for all HBTs and performing ion implantation to differentiate an emitter-down HBT from an emitter-up HBT.

Abstract: A semiconductor process includes the following steps. A fin-shaped structure is formed on a substrate. A gate structure and a cap layer are formed, wherein the gate structure is disposed across parts of the fin-shaped structure and parts of the substrate, the cap layer is on the gate structure, and the cap layer includes a first cap layer on the gate structure and a second cap layer on the first cap layer. A spacer material is formed to entirely cover the second cap layer, the fin-shaped structure and the substrate. The spacer material is etched, so that the sidewalls of the second cap layer are exposed and a spacer is formed beside the gate structure. The second cap layer is removed.

Abstract: A method for making semi-conductor nanocrystals, including at least the steps of: forming solid carbon chemical species on a semi-conductor thin layer provided on at least one dielectric layer, the dimensions and the density of the carbon chemical species formed on the semi-conductor thin layer being a function of the desired dimensions and density of the semi-conductor nanocrystals; annealing the semi-conductor thin layer, performing a dewetting of the semi-conductor and forming, on the dielectric layer, the semi-conductor nanocrystals.

Abstract: A method of forming trenches in a semiconductor device includes forming an etchant barrier layer above a first portion of a semiconductor layer. A first trench is etched in a second portion of the semiconductor layer using a first etchant. The second portion of the semiconductor layer is not disposed underneath the etchant barrier layer. The etchant barrier layer is etched through using a second etchant that does not substantially etch the semiconductor layer. A second trench is etched in the first portion of the semiconductor layer using a third etchant. The third etchant also extends a depth of the first trench.

Abstract: One method disclosed herein includes forming first, second and third gate stacks, wherein one of the gate stacks is an isolation stack positioned above an isolation structure and each of the gate stacks is comprised of three layers of hard mask material positioned above a layer of gate electrode material. The method also involves forming sidewall spacers proximate the second gate stack while the first and isolation gate stacks are masked, forming sidewall spacers proximate the first gate stack while the second and isolation gate stacks are masked, forming a polish stop layer between the plurality of gate stacks, performing another etching process on an etch stop layer, a layer of spacer material, and the second layer of hard mask material positioned above or proximate the isolation gate stack and performing a chemical mechanical polishing process to remove material positioned above an upper surface of the polish stop layer.