Abstract: Systems and methods for semiconductor device PN junction fabrication are provided. In one embodiment, a method for fabricating an electrical device having a P-N junction comprises: depositing a layer of amorphous semiconductor material onto a crystalline semiconductor base, wherein the crystalline semiconductor base comprises a crystalline phase of a same semiconductor as the amorphous layer; and growing the layer of amorphous semiconductor material into a layer of crystalline semiconductor material that is epitaxially matched to the lattice structure of the crystalline semiconductor base by applying an optical energy that penetrates at least the amorphous semiconductor material.

Abstract: To provide a method of manufacturing a semiconductor device, including: forming a thin film different from a silicon oxide film on a substrate by supplying a processing gas into a processing vessel in which the substrate is housed; removing a deposit including the thin film adhered to an inside of the processing vessel by supplying a fluorine-containing gas into the processing vessel after executing forming the thin film prescribed number of times; and forming a silicon oxide film having a prescribed film thickness on the inside of the processing vessel by alternately supplying a silicon-containing gas, and an oxygen-containing gas and a hydrogen-containing gas into the heated processing vessel in which a pressure is set to be less than an atmospheric pressure after removing the deposit.

Abstract: For solar cell fabrication, the addition of precursors to printable media to assist etching through silicon nitride or silicon oxide layer thus affording contact with the substance underneath the nitride or oxide layer. The etching mechanism may be by molten ceramics formed in situ, fluoride-based etching, as well as a combination of the two.

Abstract: Systems and methods for preparing resistive switching memory devices such as resistive random access memory (ReRAM) devices wherein both oxide and nitride layers are deposited in a single chamber are provided. Various oxide and nitride based layers in the ReRAM device such as the switching layer, current-limiting layer, and the top electrode (and optionally the bottom electrode) are deposited in the single chamber. By fabricating the ReRAM device in a single chamber, throughput is increased and cost is decreased. Moreover, processing in a single chamber reduces device exposure to air and to particulates, thereby minimizing device defects.

Abstract: A method of manufacturing a semiconductor device includes: accommodating a substrate in a processing chamber; and supplying an organosilicon-based gas into the processing chamber that is heated to form a film including silicon and carbon on the substrate. In the forming of the film including silicon and carbon, a cycle is performed a predetermined number of times. The cycle includes supplying the organosilicon-based gas into the processing chamber and confining the organosilicon-based gas in the processing chamber, maintaining a state in which the organosilicon-based gas is confined in the processing chamber, and exhausting an inside of the processing chamber.

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract: A method includes recessing isolation regions, wherein a portion of a semiconductor strip between the isolation regions is over top surfaces of the recessed isolation regions, and forms a semiconductor fin. A dummy gate is formed to cover a middle portion of the semiconductor fin. An Inter-Layer Dielectric (ILD) is formed to cover end portions of the semiconductor fin. The dummy gate is then removed to form a first recess, wherein the middle portion is exposed to the first recess. The middle portion of the semiconductor fin is removed to form a second recess. An epitaxy is performed to grow a semiconductor material in the second recess, wherein the semiconductor material is between the end portions. A gate dielectric and a gate electrode are formed in the first recess. The gate dielectric and the gate electrode are over the semiconductor material.

Abstract: A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid.

Abstract: A device fabrication method includes: (1) providing a growth substrate including a base and an oxide layer disposed over the base; (2) forming a metal layer over the oxide layer; (3) forming a stack of device layers over the metal layer; (4) performing interfacial debonding of the metal layer to separate the stack of device layers and the metal layer from the growth substrate; and (5) affixing the stack of device layers to a target substrate.

Abstract: One method disclosed herein includes forming a plurality of source/drain contacts that are conductively coupled to a source/drain region of a plurality of transistor devices, wherein at least one of the source/drain contacts is a local interconnect structure that spans the isolation region and is conductively coupled to a first source/drain region in a first active region and to a second source/drain region in a second active region, and forming a patterned mask layer that covers the first and second active regions and exposes at least a portion of the local interconnect structure positioned above an isolation region that separates the first and second active regions. The method further includes performing an etching process through the patterned mask layer to remove a portion of the local interconnect structure, thereby defining a recess positioned above a remaining portion of the local interconnect structure, and forming an insulating material in the recess.

Abstract: The invention provides a semiconductor device and a method of automatically inspecting the appearance, which achieves proper recognition of the size of a chipping occurring from an end portion of the semiconductor device toward the element forming region by an automatic appearance inspection machine, and prevents a problem of judging an appearance non-defective product as an appearance defective product. A semiconductor device includes a resin layer extending from an element forming region over a guard ring surrounding the element forming region so as to cover these except a plurality of portions of the guard ring, and a chipping extending from a chip end portion of a semiconductor device toward the end portion of the resin layer.

Abstract: Manufacturing a semiconductor device includes preparing a structure including a semiconductor substrate having a first region and a second region, a first insulating film arranged on the first region, a second insulating film arranged on the first insulating film, a third insulating film arranged on the second insulating film, a fourth insulating film arranged on the second region, a fifth insulating film arranged on the fourth insulating film, and a sixth insulating film arranged on the fifth insulating film, etching the second insulating film and the first insulating film under different etching conditions after etching the third insulating film, and continuously etching the fifth insulating film and the fourth insulating film under the same etching conditions after etching the sixth insulating film.

Abstract: Provided are methods for fabricating a semiconductor device. The methods include forming a hard mask pattern on a semiconductor substrate, forming a first trench having a first width and a second trench having a second width on the semiconductor substrate using the hard mask pattern as a mask, forming an oxide film on the hard mask pattern and the first and second trenches, forming first and second isolation films on the first and second trenches by planarizing the oxide film until the hard mask pattern is exposed, and etching the first isolation film by a first thickness by performing dry cleaning on the semiconductor substrate and etching the second isolation film by a second thickness different from the first thickness.

Abstract: Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the via formed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.

Abstract: A method of forming an insulation film on a semiconductor substrate by plasma enhanced atomic layer deposition (PEALD), includes: (i) adsorbing a non-excited non-halide precursor having four or more silicon atoms in its molecule onto a substrate placed in a reaction space; (ii) supplying an oxygen-free reactant to the reaction space without applying RF power so as to expose the precursor-adsorbed substrate to the reactant; and (iii) after step (ii), applying RF power to the reaction space while the oxygen-free reactant is supplied in the reaction space; and (iv) repeating steps (i) to (iii) as a cycle, thereby depositing an insulation film on the substrate.

Abstract: The present disclosure relates to a method of forming a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the method comprises forming a plurality of photodetectors within a front-side of a semiconductor substrate. An implant is performed on the back-side of the semiconductor substrate to form an implantation region having a doping concentration that is greater in the center than at the edges of the semiconductor substrate. The back-side of the workpiece is then exposed to an etchant, having an etch rate that is inversely proportional to the doping concentration, which thins the semiconductor substrate to a thickness that allows for light to pass through the back-side of the substrate to the plurality of photodetectors. By implanting the substrate prior to etching, the etching rate is made uniform over the back-side of the substrate improving total thickness variation between the photodetectors and the back-side of the substrate.

Abstract: An approach for providing layout designs with via routing structures is disclosed. Embodiments include: providing a gate structure and a diffusion contact on a substrate; providing a gate contact on the gate structure; providing a metal routing structure that does not overlie a portion of the gate contact, the diffusion contact, or a combination thereof; and providing a via routing structure over the portion and under a part of the metal routing structure to couple the gate contact, the diffusion contact, or a combination thereof to the metal routing structure.

Abstract: The NH3 plasma treatment by remote plasma is firstly proposed to replace the covalent bonding process during surface modification procedure that for amine bond generation.

Abstract: Disclosed are methods for co-integration of active and passive photonic devices on a planarized silicon-based photonics substrate. In one aspect, a method is disclosed that includes providing a planarized silicon-based photonics substrate comprising a silicon waveguide structure, depositing a dielectric layer over the planarized silicon-based photonics substrate, selectively etching the dielectric layer, thereby exposing at least a portion of the silicon waveguide structure, selectively etching the exposed portion of the silicon waveguide structure to form a template, using the silicon waveguide structure as a seed layer to selectively grow in the template a germanium layer that extends above the dielectric layer, and planarizing the germanium layer to form a planarized germanium layer, wherein the planarized germanium layer does not extend above the dielectric layer.

Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.