Abstract: A nitride semiconductor light emitting device includes a laminate, first and second electrodes, a conductive layer, and a phosphor layer. The laminate includes a first layer including a first electroconductive-type layer, a second layer including a second electroconductive-type layer, a light emitting layer between the first and second layers, and a nitride semiconductor. The laminate has a recessed portion extending from the first layer to the second layer in a central portion or an outer peripheral portion. The first electrode arranged on the first layer reflects light emitted from the light emitting layer. The second electrode is surrounded by the light emitting layer or on the periphery thereof and connected to a bottom surface of the recessed portion. The conductive layer is arranged on a surface of the second layer at a side opposite to the light emitting layer. The phosphor layer overlies the second layer and the conductive layer.

Abstract: A method of forming an ultra-shallow junction in a semiconductor substrate. The method includes forming an amorphous region in a semiconductor substrate by performing a pre-amorphization implant step and implanting one or more dopants in the amorphous region by performing a monolayer doping step. The semiconductor substrate is then thermally treated to activate the implanted dopant in the amorphous region to thereby form an ultra-shallow junction in the semiconductor substrate. The thermal treatment can be performed without any oxide cap overlying the implanted amorphous region.

Abstract: In a method of manufacturing a semiconductor integrated circuit device having an MEMS element over a single semiconductor chip, the movable part of the MEMS element is fixed before the formation of a rewiring. After formation of the rewiring, the wafer is diced. Then, the movable part of the MEMS element is released by etching the wafer.

Abstract: A method of tailoring the dopant profile of a workpiece by modulating one or more operating parameters is disclosed. In one embodiment, the workpiece may be a solar cell and the desired dopant profile may include a heavily doped surface region and a highly doped region. These two regions can be generated by varying one or more of the parameters of the ion implanter. For example, the extraction voltage may be changed to affect the energy of the implanted ions. The ionization energy can be changed to affect the species of ions being generated from the source gas. In another embodiment, the source gasses that are ionized may be changed to affect the species being generated. After the implant has been performed, thermal processing is performed which minimizes the diffusion of the ions in the workpiece.

Abstract: A semiconductor lighting device may include a substrate populated with at least one semiconductor light source, wherein at least one reflective surface region of the substrate is covered with a light-reflecting layer, and wherein the light-reflecting layer has an aluminum carrier coated in a reflection-intensifying manner.

Abstract: The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thic

Abstract: A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.

Abstract: A method for manufacturing an electronic device and an electronic device are disclosed. In an embodiment the method comprises forming an opening in an isolation layer, isotropically etching the opening thereby forming an extended opening with curved sidewalls, and forming a conductive material in the opening.

Abstract: A method of fabricating a semiconductor device includes providing an assembly substrate including a split plane defining a handle region and a transfer region, a film layer coupled to the transfer region, and one or more active devices coupled to the film layer. The method also includes providing a device substrate including one or more bonding regions and joining the assembly substrate to the device substrate. The method further includes splitting the assembly substrate to remove the handle region.

Abstract: A mask set and method for forming FinFET semiconductor devices provides a complementary set of fin-cut masks that are used in DPT (double patterning technology) to remove fins from non-active areas of a semiconductor device, after the fins are formed. Adjacent fins, or adjacent groups of fins, are removed using pattern features from different ones of the multiple fin-cut masks.

Abstract: Embodiments related to methods for forming a film stack on a substrate are provided. One example method comprises exposing the substrate to an activated oxygen species and converting an exposed surface of the substrate into a continuous monolayer of a first dielectric material. The example method also includes forming a second dielectric material on the continuous monolayer of the first dielectric material without exposing the substrate to an air break.

Abstract: A FinFET device and a method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a substrate including a fin structure, the fin structure including a first and a second fin. The FinFET device further includes a shallow trench isolation (STI) feature disposed on the substrate and between the first and the second fins. The FinFET device further includes a gate dielectric disposed on the first and the second fins. The FinFET device further includes a gate structure disposed on the gate dielectric. The gate structure traverses the first fin, the second fin, and the STI feature between the first fin and the second fin and has a longitudinal stepped profile.

Abstract: A method for manufacturing a dopant layer of a solar cell according to an embodiment of the invention includes: ion-implanting a dopant to a substrate; and heat-treating for an activation of the dopant. In the heat-treating for the activation, the substrate is heat-treated at a first temperature after an anti-out-diffusion film is formed at a temperature lower than the first temperature under a first gas atmosphere.

Abstract: A thin film transistor having low off-state current and excellent electrical characteristics can be manufactured. In an inverted staggered thin film transistor including a semiconductor film in which at least a microcrystalline semiconductor region and an amorphous semiconductor region are stacked, a conductive film and an etching protective film are stacked over the semiconductor film; a mask is formed over the etching protective film; first etching treatment in which the etching protective film, the conductive film, and the amorphous semiconductor region are partly etched is performed; then, the mask is removed. Next, second etching treatment in which the exposed amorphous semiconductor region and the microcrystalline semiconductor region are partly dry-etched is performed using the etched etching protective film as a mask so that the microcrystalline semiconductor region is partly exposed to form a back channel region.

Abstract: A semiconductor device includes a substrate, a gate electrode, an insulating layer, a source electrode, a drain electrode, a semiconductor channel layer, a first passivation layer and a second passivation layer. The gate is formed on the substrate. The insulating layer covers the gate electrode. The source electrode and the drain electrode are positioned on the insulating layer. The semiconductor channel layer is disposed on the insulating layer, and connects the source electrode and the drain electrode. The first passivation layer covers the source electrode, the drain electrode and the semiconductor channel layer. The first passivation layer includes silicon oxide. The second passivation layer is disposed on the first passivation layer. The second passivation layer includes silicon nitride that has a hydrogen concentration of about 2.0×1022 atom/cm3 to about 3.11×1022 atom/cm3.

Abstract: A loading port includes a housing and a plurality of stations defined in the housing configured to receive a front opening universal pod (FOUP). The loading port further includes a connector configured to receive an inert gas. At least one of the plurality of stations is configured to deliver the inert gas to the FOUP to purge an interior of the FOUP of moisture. A system including the loading port and a method of using the system are also described.

Abstract: A method for manufacturing a dopant layer of a solar cell according to an embodiment of the invention includes: ion-implanting a dopant to a substrate; and heat-treating for an activation of the dopant. In the heat-treating for the activation, the substrate is heat-treated at a first temperature after an anti-out-diffusion film is formed at a temperature lower than the first temperature under a first gas atmosphere.

Abstract: A fin field effect transistor (FET) including a fin structure and a method for forming the fin FET are provided. In an exemplary method, the fin FET can be formed by forming at least one fin seed, including a top surface and sidewalls, on a substrate. A first semiconductor layer can then be formed at least on the sidewalls of the at least one fin seed. A second semiconductor layer can be formed on the first semiconductor layer. The second semiconductor layer and the at least one fin seed can be made of a same material. The first semiconductor layer can be removed to form a fin structure including the at least one fin seed and the second semiconductor layer.

Abstract: Among other things, one or more image sensors and techniques for guiding light towards a photodiode are provided. An image sensor comprises a metal grid configured to direct light towards a corresponding photodiode and away from other photodiodes. The image sensor also comprises a dielectric grid and a filler grid over the metal grid to direct light towards the corresponding photodiode and away from other photodiodes, where the filler grid has a different refractive index than the dielectric grid. In this way, crosstalk, otherwise resulting from detection of light by incorrect photodiodes, is mitigated.

Abstract: In one general aspect, a method can include implanting a first dopant, simultaneously, in a portion of a laterally diffused metal oxide semiconductor (LDMOS) device and in a portion of a resistor device included in a semiconductor device. The method can also include implanting a second dopant, simultaneously, in a portion of the LDMOS device and in a portion of a bipolar junction transistor (BJT) device in the semiconductor device.