Abstract: Angled directional ion beams are directed to sidewalls of a gate structure that straddles at least one semiconductor fin. The directions of the angled directional ion beams are contained within a vertical plane that is parallel to the sidewalls of the at least one semiconductor. A pair of gate spacers are formed on sidewalls of the gate structure by accumulation of the deposited dielectric material from the angled directional ion beams and without use of an anisotropic etch, while the sidewalls of the semiconductor fins parallel to the directional ion beams remain physically exposed. A selective epitaxy process can be performed to form raised active regions by growing a semiconductor material from the sidewalls of the semiconductor fins.

Abstract: Electrodes of a solar cell formed by an active solder and a method therefor are provided. The method includes steps of: providing a solar cell substrate; providing an active solder having at least one type of soldering alloy mixed with 6 wt % or less of at least one type of active component and 0.01-2.0 wt % of at least one type of rare earth element (Re); firstly melting the active solder at a temperature lower than 450° C.; then applying the molten active solder on the solar cell substrate (or firstly applying and then melting); and cooling to solidify the active solder, so as to form an electrode pattern.

Abstract: The present invention relates to coated binary and ternary chalcogenide nanoparticle compositions that can be used as copper zinc tin chalcogenide precursor inks. In addition, this invention relates to coated substrates comprising binary and ternary chalcogenide nanoparticle compositions and provides processes for manufacturing these coated substrates. This invention also relates to compositions of copper zinc tin chalcogenide thin films and photovoltaic cells comprising such films. In addition, this invention provides processes for manufacturing copper zinc tin chalcogenide thin films, as well as processes for manufacturing photovoltaic cells incorporating such films.

Abstract: A manufacture includes an IC comprising a stacking of a semiconducting substrate, a buried insulating layer, and a semiconducting layer, a first electronic component formed in and/or on the semiconductor layer, a bias circuit to generate a first bias voltage, first and second via-type interconnections, to which the bias circuit applies a same bias voltage equal to the first bias voltage, a first insulation trench separating the first electronic component from the first and second interconnections, a first ground plane having a first type of doping, placed beneath the buried insulating layer plumb with the first electronic component, and extending beneath the first insulation trench and up into contact the first interconnection, and a first well having a second type of doping opposite that of the first type, plumb with the first ground plane, and extending beneath the first insulation trench and up into contact with the second interconnection.

Abstract: Silicon and silicon germanium fins are formed on a semiconductor wafer or other substrate in a manner that facilitates production of closely spaced nFET and pFET devices. A patterned mandrel layer is employed for forming one or more recesses in the wafer prior to the epitaxial growth of a silicon germanium layer that fills the recess. Spacers are formed on the side walls of the patterned mandrel layer followed by removal of the mandrel layer. The exposed areas of the wafer and silicon germanium layer between the spacers are etched to form fins usable for nFET devices from the wafer and fins usable for pFET devices from the silicon germanium layer.

Abstract: To establish a processing technique in manufacture of a semiconductor device including an In—Sn—Zn—O-based semiconductor. An In—Sn—Zn—O-based semiconductor layer is selectively etched by dry etching with the use of a gas containing chlorine such as Cl2, BCl3, SiCl4, or the like. In formation of a source electrode layer and a drain electrode layer, a conductive layer on and in contact with the In—Sn—Zn—O-based semiconductor layer can be selectively etched with little removal of the In—Sn—Zn—O-based semiconductor layer with the use of a gas containing oxygen or fluorine in addition to a gas containing chlorine.

Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.

Abstract: A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate.

Abstract: Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (RF) power supply. Each step is analyzed with the nominal frequency, and the analysis determines if any step produces instability at the nominal frequency. The operating frequency is adjusted, for one or more of the steps, when the instability in the one or more steps exceeds a threshold. The adjustment acts to find an approximate minimum level of instability. A second recipe is constructed after the adjustment, such that at least one of the steps includes a respective operating frequency different from the nominal frequency. The second recipe is used to etch the one or more layers disposed over the substrate in the semiconductor processing chamber.

Abstract: Embodiments of the invention provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in magnetoresistive random access memory applications. In one embodiment, a method of forming a MTJ structure on a substrate includes providing a substrate having a insulating tunneling layer disposed between a first and a second ferromagnetic layer disposed on the substrate, wherein the first ferromagnetic layer is disposed on the substrate followed by the insulating tunneling layer and the second ferromagnetic layer sequentially, supplying an ion implantation gas mixture to implant ions into the first ferromagnetic layer exposed by openings defined by the second ferromagnetic layer, and etching the implanted first ferromagnetic layer.

Abstract: Provided are a semiconductor device manufacturing method and a substrate processing apparatus that are capable of increasing a work function of a film to be formed, in comparison with a related art. A cycle including (a) supplying a metal-containing gas into a processing chamber where a substrate is accommodated (b) supplying a nitrogen-containing gas into the processing chamber; and (c) supplying one of an oxygen-containing gas, a halogen-containing gas and a combination thereof into the processing chamber, is performed a plurality of times to form a metal-containing film on the substrate.

Abstract: A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material.

Abstract: In one embodiment, a semiconductor package includes a semiconductor chip having a first contact region on a first major surface and a second contact region on an opposite second major surface. The semiconductor chip is configured to regulate flow of a current from the first contact region to the second contact region. An encapsulant is disposed at the semiconductor chip. A first contact plug is disposed within the encapsulant and coupled to the first contact region. A second side conductive layer is disposed under the second major surface and coupled to the second contact region. A through via is disposed within the encapsulant and coupled to the second side conductive layer. The first contact plug and the through via form terminals above the first major surface for contacting the semiconductor package.

Abstract: A method of manufacturing a semiconductor device including: mounting a substrate on a substrate mounting member that is disposed in a reaction container; heating the substrate at a predetermined processing temperature and supplying a first gas and a second gas to the substrate to process the substrate; stopping supply of the first gas and the second gas, and supplying an inert gas into the reaction container; and unloading the substrate to outside the reaction container.

Abstract: A method and apparatus are provided for recessing a channel region of the PFET and epitaxially growing channel SiGe in the recessed region inside of a horizontally oriented processing furnace. Embodiments include forming an n-channel region and a p-channel region in a front side of a wafer and at least one additional wafer, the n-channel and p-channel regions corresponding to locations for forming an NFET and a PFET, respectively; placing the wafers inside a horizontally oriented furnace having a top surface and a bottom surface, with the wafers oriented vertically between the top and bottom surfaces; recessing the p-channel regions of the wafers inside the furnace; and epitaxially growing cSiGe without hole defects in the recessed p-channel regions inside the furnace.

Abstract: Each of the step of forming a first variable resistance layer (18a) and the step of forming a second variable resistance layer (18b) includes performing a cycle once or plural times, the cycle consisting of a first step of introducing a source gas composed of molecules containing atoms of a transition metal; a second step of removing the source gas after the first step; a third step of introducing a reactive gas to form a transition metal oxide after the second step; and a fourth step of removing the reactive gas after the third step. The step of forming the first variable resistance layer (18a) is performed in a state in which the substrate is kept at a temperature at which a self-decomposition reaction of the source gas does not occur.

Abstract: A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process.

Abstract: Field effect transistors including a source region and a drain region on a substrate, a fin base protruding from a top surface of the substrate, a plurality of fin portions extending upward from the fin base and connecting the source region with the drain region, a gate electrode on the fin portions, and a gate dielectric between the fin portions and the gate electrode may be provided. A top surface of the substrate may include a plurality of grooves (e.g., a plurality of convex portions and a plurality of concave portions). Further, a device isolation layer may be provided to expose upper portions of the plurality of fin portions and to cover top surfaces of the plurality of grooves.

Abstract: A method includes forming a plurality of image sensors on a front side of a semiconductor substrate, and forming a dielectric layer on a backside of the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The dielectric layer is patterned into a plurality of grid-filling regions, wherein each of the plurality of grid-filling regions overlaps one of the plurality of image sensors. A metal layer is formed on top surfaces and sidewalls of the plurality of grid-filling regions. The metal layer is etched to remove horizontal portions of the metal layer, wherein vertical portions of the metal layer remain after the step of etching to form a metal grid. A transparent material is filled into grid openings of the metal grid.

Abstract: A method of forming a hydrophobic surface on a semiconductor device structure. The method comprises forming at least one structure having at least one exposed surface comprising titanium atoms. The at least one exposed surface of at least one structure is contacted with at least one of an organo-phosphonic acid and an organo-phosphoric acid to form a material having a hydrophobic surface on the at least one exposed surface of the least one structure. A method of forming a semiconductor device structure and a semiconductor device structure are also described.