Patents Examined by Reginald Bragdon
  • Patent number: 10140022
    Abstract: Exemplary embodiments provide subsidiary volume management. In one embodiment, a storage system comprises: a memory being operable to store information of a plurality of logical unit groups, each of the plurality of logical unit groups including information of an administrative logical unit (LU) and information of one or more subsidiary LUs to be accessed from a virtual machine on a computer; and a controller being operable to create or select an administrative LU and to inform the computer of the created or selected administrative LU according to evaluation of a subsidiary LU which relates to another administrative LU, when the controller receives a command from the computer to said another administrative LU.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 27, 2018
    Assignee: Hitachi, Ltd.
    Inventor: Akio Nakajima
  • Patent number: 10140051
    Abstract: Performing a file backup includes receiving a file to backup from a source machine and performing a write operation to write the file to a mount point in a file system on a backup server. The backup also includes intercepting a block-level data block to be written which is generated by the write operation; and writing the block-level data block to a corresponding, respective block of a disk image file having a plurality of blocks.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: November 27, 2018
    Assignee: CA, Inc.
    Inventors: Chuanqi Sun, Zhiye Wang
  • Patent number: 10133484
    Abstract: A hierarchal storage management method is provided. The method includes detecting a first portion of a first file being deleted from a hybrid storage device including a hard disk drive (HDD) memory device, a solid state drive (SSD) memory device, and an archival storage memory device. A first set of memory blocks associated with the first portion of the first file is identified. The first set of memory blocks are determined to reside on the SSD memory device. In response, the first set of memory blocks are transferred from the SSD memory device to a first portion of the hybrid storage device.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: November 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Blaine H. Dolph, Nataraj Nagaratnam, Sandeep R. Patil, Riyazahamad M. Shiraguppi
  • Patent number: 10120791
    Abstract: A data read apparatus includes a nonvolatile memory comprising a plurality of blocks, each of the blocks including an area storing block information, in which a position of a next block is written, or storing the block information and file management information, and an area storing actual data; a volatile memory; a power-on circuit configured to turn on supply of power to the nonvolatile memory and the volatile memory; and a processor. The processor is configured to: read out the block information stored in each of the blocks of the nonvolatile memory, or the block information and the file management information, when the supply of power was turned on by the power-on circuit, and register the read-out block information, or the block information and the file management information, in the volatile memory as file position information.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: November 6, 2018
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Shunsuke Yamada
  • Patent number: 10114568
    Abstract: A method for regulating a flow of data to backend storage devices includes generating, at a host system, writes intended for a backend storage volume. The method receives the writes into a first level cache of a storage virtualization appliance. The method further determines whether destaging the writes directly from the first level cache to the backend storage volume would cause a limit associated with the backend storage volume to be exceeded. If destaging the writes directly from the first level cache to the backend storage volume would cause the limit to be exceeded, the method destages the writes from the first level cache to a second level cache of the storage virtualization appliance. Otherwise, the method destages the writes directly from the first level cache to the backend storage volume. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: October 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: John P. Agombar, Ian Boden, Gordon D. Hutchison, Lee J. Sanders
  • Patent number: 10108342
    Abstract: A SSD and a method for reducing use of DRAM in the SSD are disclosed. The method includes the steps of: A. providing a referring table in a DRAM module of a SSD; B. providing a logical-to-physical address table in the DRAM module; C. receiving a command for accessing a target data in a target logical address of the SSD; D. checking if one physical address is stored in the logical-to-physical address table; E. executing the command by using the mapping data in the subgroup or copying a corresponding subgroup including one mapping data for the target logical address from the mapping table to the DRAM module via the referring table; and; and F. adding a target physical address of the DRAM module where the mapping data for the target logical address is stored to the logical-to-physical address table so that the target logical address is able to correspond thereto.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: October 23, 2018
    Assignee: Storart Technology Co. Ltd.
    Inventor: Hou Yun Lee
  • Patent number: 10101934
    Abstract: Described herein are embodiments of a process that can be used to balance the allocation of primary memory between different types of information. In some embodiments, the memory allocation is balanced dynamically based on observed I/O patterns. Related system embodiments are also described.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: October 16, 2018
    Assignee: EMC Corporation
    Inventors: Tal Ben-Moshe, Eli Dorfman, Kirill Shoikhet, David Krakov, Roman Vainbrand, Noa Cohen
  • Patent number: 10102147
    Abstract: In a system in which a plurality of computing elements share a cache, each computing element owns a stripe of the cache. Each stripe contains cache objects that are accessible to all computing elements but managed only by the owning computing element. Each computing element maintains an LRU FIFO queue in local memory for the cache objects owned by that computing element. Each computing element also maintains a separate hash table in local memory for each other computing element. The hash tables indicate access to cache objects that are owned by those other computing elements. Each computing element updates its LRU FIFO queue when it accesses cache objects that it owns. The hash tables are periodically distributed by all computing elements via RDMA so that the LRU FIFO queues of all computing elements can be updated based on accesses to owned cache objects by other non-owner computing elements.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: October 16, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Gabriel BenHanokh, Andrew Chanler, Felix Shvaiger, Hongliang Tang, Arieh Don
  • Patent number: 10095418
    Abstract: In a hierarchical storage system, blocks of data selected for auto-tiering migration, are selected based on dynamically adjusted group sizes. Contiguous blocks are organized into default groups. I/O activity of the blocks in a group is monitored. Based on the I/O activity, the default groups may be sub-divided into smaller sub-groups or combined into larger groups, to separate as much as practical, contiguous series of cooler blocks and contiguous series of hotter blocks into respective focused (concentrated) groups or sub-groups. The concentrated group or sub-group may then be migrated according to the average I/O activity of the included blocks. Group configurations are continually and dynamically adjusted according to changing I/O conditions.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yongjie Gong, Shuang Shuang Li, Yang Liu, Mei Mei, Xue Qiang Zhou
  • Patent number: 10095614
    Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: October 9, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Yu-Wei Chyan, Jiyun-Wei Lin
  • Patent number: 10089242
    Abstract: Disclosed are systems and methods for managing memory. A memory management system may include a table having multiple virtual memory addresses. Each virtual memory address may correspond to a physical memory address and data that identifies a type of memory device corresponding to the physical memory address. The physical memory device can be used to access the memory device when a table hit occurs.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: October 2, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Dean A. Klein
  • Patent number: 10061798
    Abstract: A system and method for managing tables in a storage system is described.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: August 28, 2018
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Joseph S. Hasbani, John Hayes, Ethan Miller, Cary Sandvig
  • Patent number: 10042710
    Abstract: Systems and methods of backing up data to a replication target such that the data is recoverable from the replication target when a source application and one or more other intermediary replication targets are unavailable. A first deduplicated data object associated with an application is received at a first intermediary copy data management system based on a first schedule. The first deduplicated data object is replicated to generate at least one of a second deduplicated data object at a second copy data management system according to a second schedule.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: August 7, 2018
    Assignee: Actifio, Inc.
    Inventors: Madhav Mutalik, Satya Sri Kanth Palaparthi
  • Patent number: 10033790
    Abstract: A system includes a resource adapter module in the form of executable code by a processor, the resource adapter module to, interact with an application running on an application server by receiving calls from applications, and provide communication between the application and any JMS provider by relaying the calls to the JMS provider.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: July 24, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Dongbo Xiao, Qiang Liu, John Leinaweaver, Jefferey Steidl, Paul Parkinson, Thomas E. Barnes, Vivekananda Maganty
  • Patent number: 10013210
    Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller equally distributes the TLC-data blocks into three regions. In a first stage, the controller determines a first TLC-data block corresponding to the logic address of a prewrite data sector, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data. When the first TLC-data block does not have valid data, the controller selects a second TLC-data block and a third TLC-data block from the regions other than the first region for writing the prewrite data sector, into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: July 3, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Chien-Cheng Lin, Jie-Hao Lee
  • Patent number: 10013313
    Abstract: Systems and methods of performing backup of databases and associated logs with one schedule such that a backup of both a database and its associated log can be restored or recovered to a desired point in time. A backup request associated with a backup type is received and defined by a service level agreement. The service level agreement includes a combined schedule for backing up both data stored in the database and log data associated with a database.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: July 3, 2018
    Assignee: Actifio, Inc.
    Inventors: Xiangdong Zhang, Uday Tekade, Sachindra Kumar, Madhav Mutalik
  • Patent number: 10007461
    Abstract: Accesses to a number of data blocks stored in a distributed storage are observed. Following observation of the accesses, the stored data blocks are redistributed. In one aspect, redistribution of the data blocks includes determining the access patterns for one or more of the data blocks based on the observed accesses, and determining the storage sizes for the one or more data blocks. Thereafter, based on the determined access patterns and determined storage sizes, the one or more data blocks are sorted. Subsequently, the one or more data blocks are redistributed or rebalanced across a number of storage devices of the distributed storage based on the sorting. In one aspect, the one or more data blocks are redistributed according to either a uniform distribution scheme or a proportional distribution scheme.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: June 26, 2018
    Assignee: Quantcast Corporation
    Inventors: Silvius V. Rus, Michael Ovsiannikov
  • Patent number: 10007619
    Abstract: Systems and methods relate to performing address translations in a multithreaded memory management unit (MMU). Two or more address translation requests can be received by the multithreaded MMU and processed in parallel to retrieve address translations to addresses of a system memory. If the address translations are present in a translation cache of the multithreaded MMU, the address translations can be received from the translation cache and scheduled for access of the system memory using the translated addresses. If there is a miss in the translation cache, two or more address translation requests can be scheduled in two or more translation table walks in parallel.
    Type: Grant
    Filed: September 20, 2015
    Date of Patent: June 26, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Paul Christopher John Wiercienski, Carlos Javier Moreira, Alexander Miretsky, Meghal Varia, Kyle John Ernewein, Manokanthan Somasundaram, Muhammad Umar Choudry, Serag Monier Gadelrab
  • Patent number: 9996296
    Abstract: An electronic control unit includes: a nonvolatile memory capable of erasing data in units of erasure blocks and also writing data in units of write blocks smaller than the erasure blocks; and a processor. In response to a data rewrite request from outside, the processor of the electronic control unit erases data in a portion of the nonvolatile memory in units of erasure blocks and writes data into the portion of the nonvolatile memory in units of write blocks. The amount of data sent to the electronic control unit from outside is thereby decreased and the time needed to rewrite data in the nonvolatile memory is reduced.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 12, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Toshifumi Miyake, Yusuke Abe, Koji Yuasa, Toshihisa Arai
  • Patent number: 9977598
    Abstract: The present invention provides a method for managing memory space in an electronic device including: selecting a candidate page from a first memory space for swapping the candidate page out of the first memory space into the second memory space; compressing the candidate page to obtain a first compressed page and a first hash value of the first compressed page; performing a comparison using the first hash value of the first compressed page and the hash values of the pages stored in a second memory space to find whether the pages have the same content as the first compressed page or the candidate page; and if a page is found to have the same content as the first compressed page or the candidate page, mapping a virtual address of the first compressed page or the candidate page to the found page.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: May 22, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chung-Jung Lee, Nicholas Ching Hui Tang, Chin-Wen Chang, Min-Hua Chen, Chih-Hsuan Tseng