Abstract: A method of operating a controller includes receiving write data having chunks from a host, assigning each of finger prints to each of the chunks, counting the number of duplications of each of the finger prints, and changing a physical address assigned to each of first finger prints among the finger prints based on a count value of each of the finger prints based on a count value of each of the finger prints, and the physical address is assigned by a flash translation layer (FTL).

Abstract: A method for managing storage allocation includes adaptively determining, by a storage device processor, a region width across disk spaces for a group of storage devices that is inversely proportional to a number of nodes sharing a particular storage device. An adaptive storage device allocation region of the particular storage device is created based on the determined region width across the disk spaces for the group of storage devices.

Abstract: Embodiments include methods, apparatus, and systems for managing resources in a physical storage library behind a virtual storage library. In one embodiment, priorities are assigned to copy applications and rules determine which when applications are assigned to resources in the physical storage library.

Abstract: A backup storage system and methods implemented by the backup storage system are disclosed. The backup software performs a plurality of backup operations to backup one or more data objects according to a backup schedule. The backup operations may be alternated across a plurality of backup storage devices, and each of the backup operations may operate to store a respective backup data set on one of the backup storage devices. In performing the plurality of backup operations, the backup storage system may create the backup data sets such that each respective backup storage device can be used independently of the other backup storage device(s) to perform a complete recovery of the one or more data objects to any point in time that corresponds to any respective backup data set stored on the respective backup storage device.

Abstract: A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.

Abstract: Techniques to send and receive access commands are provided. The access commands may include an expected media position. The expected media position may be compared to an actual media position.

Abstract: A computing memory includes an execution unit and an access processor coupled with a memory system, where the execution unit and the access processor are logically separated units. The execution unit is for processing operand data. The access processor is for providing operand data and configuration data to the execution unit. The access processor reads operand data from the memory system and sends the operand data to the execution unit. The execution unit executes the operand data according to the provided configuration data. The access processor includes information about execution times of operations of the execution unit for the provided configuration. The access processor reserves time-slots for writing execution unit results provided by the execution unit into selected locations in the memory system based on the information about the execution times, upon sending at least one of the operand data and the configuration data to the execution unit.

Abstract: In order to ensure that a normally-off computer connected to a volatile component operates normally and rapidly after operation of turning-on/off of a power supply is executed, a computation processing device which has nonvolatile registers and which is able to continue processing of data retained in the device after the power supply is turned off/on without retracting the data to an external device includes at least: a central processing unit including the nonvolatile registers; a connection unit for a volatile component which saves internal information in a volatile storage element thereof; a nonvolatile storage unit for saving a return program from a power-off state of the volatile component; and an inspection unit notifying that a potential of the power supply in the computation processing device has reached an operation potential at a time of return.

Abstract: During a startup process of a host, a request is sent to a DSD to identify storage media of the DSD. Identification information is received from the DSD before executing a driver on the host for interfacing with the DSD. The identification information identifies a first storage media of the DSD in response to the request. A second storage media is later identified using the driver.

Abstract: Embodiments of the present invention provide an approach for memory protection at a level of granularity above a “page” level (e.g., enhancing the protection provided by a memory key-based system). The approach further provides such a level of protection at a process or task level by associating the physical page key with a virtual key that corresponds to a particular process/task. When access to the data is requested for a particular process or task, it is determined if a protection bit for the data is set, and if the physical page keys and/or virtual keys submitted pursuant to the request match that previously stored for the data and process/task. If so, access to the data is allowed for the particular process/task.

Abstract: A cross-page prefetching method, apparatus, and system are disclosed, which can improve a prefetching hit ratio of a prefetching device, and further improve efficiency of memory access. The method includes: receiving an indication message, sent by a cache, that a physical address is missing, where the indication message carries a mapped-to first physical address and contiguity information of a first physical page to which the first physical address belongs; acquiring a prefetching address according to the first physical address and a step size that is stored in a prefetching device; and if a page number of a physical page to which the prefetching address belongs is different from a page number of the first physical page, and it is determined, according to the contiguity information of the first physical page, that the first physical page is contiguous, prefetching data at the prefetching address.

Abstract: A garbage collection method of a data storage system having storage devices is provided. The method includes determining whether a garbage collection is needed in one of the storage devices, transferring a multicast garbage collection command from one of the storage devices to at least one other storage device in a write group through a multicast operation, and performing the garbage collection in one of the storage devices.

Abstract: According to one or more embodiments of the disclosure, systems and methods for reducing power consumption in a memory architecture are provided. In one embodiment, a method may include determining a transition from a first power state to a second power state. The method may also include determining, using a page location identifier to access a page location table, a first dirty memory page indication. Furthermore, the method may include copying data stored in a first memory location in a volatile memory corresponding to the page location identifier to a second memory location in a non-volatile memory corresponding to the page location identifier. The method may also include deactivating the volatile memory.

Abstract: A cache memory apparatus includes a tag comparator configured to compare upper bits of each of pieces of tag data included in a set indicated by a set address that is received with upper bits of a tag address that is received, compare other bits of each of the pieces of the tag data with other bits of the tag address, and determine whether there is a cache hit or a cache miss based on results of the comparisons, and an update controller configured to, in response to the cache miss, determine, as an update candidate, a piece of cache data included in the set and corresponding to the pieces of the tag data, based on the result of the comparison of the upper bits of each of the pieces of the tag data and the upper bits of the tag address, and update the update candidate with new data.

Abstract: A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

Abstract: A cache device may include a first cache including a first set and a plurality of ways corresponding to the first set, and a second cache including a second set and a plurality of ways corresponding to the second set. The second set is related with the first set depending on a vacancy of the ways of the first set.

Abstract: Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Abstract: A first feature (e.g., chart or table) includes a reference to a dynamic pointer. Independently, the pointer is defined to point to a second feature (e.g., a query). The first feature is automatically updated to reflect a current value of the second feature. The reference to the pointer and pointer definition are recorded in a central registry, and changes to the pointer or second feature automatically cause the first feature to be updated to reflect the change. A mapping between features can be generated using the registry and can identify interrelationships to a developer. Further, changes in the registry can be tracked, such that a developer can view changes pertaining to a particular time period and/or feature of interest (e.g., corresponding to an operation problem).

Abstract: Systems and methods for data storage management technology that enables a guest module of a virtual machine to indicate an order in which a host module should write data from physical memory to a secondary storage. An example method may comprise: identifying, by a processing device executing a host module, a plurality of modifications to physical memory made by a plurality of direct access operations executed by a guest module of a virtual machine; determining, by the host module, an order of the plurality of modifications to physical memory; receiving, by the host module, a synchronization request from the guest module; and responsive to the synchronization request, copying, by the host module, data from the physical memory to a secondary storage in view of the order of the plurality of modifications.

Abstract: Method and systems for a storage system are provided. Simulated cache blocks of a cache system are tracked using cache metadata while performing a workload having a plurality of storage operations. The cache metadata is segmented, each segment corresponding to a cache size. Predictive statistics are determined for each cache size using a corresponding segment of the cache metadata. The predictive statistics are used to determine an amount of data that is written for each cache size within certain duration. The process then determines if each cache size provides an endurance level after executing a certain number of write operations, where the endurance level indicates a desired life-cycle for each cache size.