Patents Examined by Reginald Bragdon
  • Patent number: 9910614
    Abstract: A method of allocating data to a storage block included in a storage network may include determining a plurality of characteristics associated with a storage block included in a storage network. The plurality of characteristics may include storage capacity of the storage block, available storage space of the storage block, likelihood of loss of data stored on the storage block, availability of the storage block with respect to the storage network, and use of the storage block. The method may further include allocating data to the storage block based on the plurality of characteristics.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: March 6, 2018
    Assignee: LYVE MINDS, INC.
    Inventors: Christian M. Kaiser, Peter D. Stout, Ain McKendrick, Timothy Bucher, Jeff Ma, Randeep Singh Gakhal, Rick Pasetto, Stephen Sewerynek
  • Patent number: 9910611
    Abstract: A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a protection key register comprising a plurality of fields. Each field comprising a set of bits reflecting a memory access permission for each of a plurality of memory domains. The memory management unit also includes a plurality of protection key mask registers. Each of the protection key mask registers comprising a mask having a plurality of bits, each bit reflecting an access permission to a corresponding field of the protection key register by a code page residing in a memory domain of the plurality of memory domains identified by an index of the protection key mask register.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 6, 2018
    Assignee: Intel Corporation
    Inventors: David A. Koufaty, Ravi L. Sahita
  • Patent number: 9911485
    Abstract: A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.
    Type: Grant
    Filed: April 3, 2014
    Date of Patent: March 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Deepti Vijayalakshmi Sriramagiri, Jung Pill Kim, Jungwon Suh, Xiangyu Dong
  • Patent number: 9898407
    Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
  • Patent number: 9898303
    Abstract: A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 20, 2018
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 9891860
    Abstract: A method is used in managing copying of data in storage systems. A request is received to copy a portion of a source logical object to a target logical object. The source and target logical objects are subject to a deduplicating technique. The portion of the source logical object is copied to the target logical object by updating metadata of the target logical object. The target logical object shares the portion of the source logical object.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: February 13, 2018
    Assignee: EMC IP Holding Company, LLC.
    Inventors: Diane M. Delgado, Lawrence Yetto, Christopher Seibel, John F. Gillono, Philippe Armangau, Alexei Karaban
  • Patent number: 9892039
    Abstract: A method and apparatus for performing non-temporal write combining using existing cache resources is disclosed. In one embodiment, a method includes executing a first thread on a processor core, the first thread including a first block initialization store (BIS) instruction. A cache query may be performed responsive to the BIS instruction, and if the query results in a cache miss, a cache line may be installed in a cache in an unordered dirty state in which it is exclusively owned by the first thread. The first BIS instruction and one or more additional BIS instructions may write data from the first processor core into the first cache line. After a cache coherence response is received, the state of the first cache line may be changed to an ordered dirty state in which it is no longer exclusive to the first thread.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: February 13, 2018
    Assignee: Oracle International Corporation
    Inventors: Mark Luttrell, David Smentek, Ramaswamy Sivaramakrishnan, Serena Leung
  • Patent number: 9892057
    Abstract: In a network element a decision apparatus has a plurality of multi-way hash tables of single size and double size associative entries. A logic pipeline extracts a search key from each of a sequence of received data items. A hash circuit applies first and second hash functions to the search key to generate first and second indices. A lookup circuit reads associative entries in the hash tables that are indicated respectively by the first and second indices, matches the search key against the associative entries in all the ways. Upon finding a match between the search key and an entry key in an indicated associative entry. A processor uses the value of the indicated associative entry to insert associative entries from a stash of associative entries into the hash tables in accordance with a single size and a double size cuckoo insertion procedure.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: February 13, 2018
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Gil Levy, Salvatore Pontarelli, Pedro Reviriego
  • Patent number: 9892043
    Abstract: A computer system comprising multiple nodes, each node comprising a plurality of processors and a local cache hierarchy, suppresses local cache coherency of a node operations or global cache coherency operations between nodes based on the coherency request being a global or local request, and the state of the cache line at the node.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Garrett Michael Drapala, William J Lewis, Pak-kin Mak, Robert J Sonnelitter, III
  • Patent number: 9891866
    Abstract: Methods and systems are described herein to provide efficient data retrieval in a data storage system. Specifically, in cases where users of a data storage system are not overly sensitive to data retrieval time, such as the case for backup and archival data storage systems, random read requests may be fulfilled as part of sequential reads to reduce I/O operations. A data storage system may be divided into data storage zones. Sequential reads may be performed for data stored in those data storage zones with pending data retrieval requests. Data retrieval requests may be fulfilled based at least in part on the sequentially-read data.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: February 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Colin L. Lazier, Kestutis Patiejunas
  • Patent number: 9891847
    Abstract: A storage device with a memory may improve yield by reducing the allocation of blocks for secondary writes in a dual programming system. In a dual programming system, all host writes are written to both a primary copy and to a secondary copy. If the secondary copy blocks that are available have a higher endurance, then the overall allocation of available blocks for use as a secondary copy block can be reduced (improving yield). In one embodiment, utilizing different trim parameters for the secondary copy blocks may be used to increase the endurance for those blocks. Before programming the secondary copy, the trim parameters may be adjusted to increase endurance and after programming the secondary copy, the trim parameters may be adjusted back to the default value that is used when programming the primary copy.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: February 13, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Abhijeet Manohar, Muralitharan Jayaraman
  • Patent number: 9891865
    Abstract: A method of providing special functions includes receiving from a host a first normal command and a first address, and identifying a first special function based on the first normal command and the first address when the first address is in an address range established for special functions according to a predefined rule.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joon-Ho Lee
  • Patent number: 9892032
    Abstract: A method and system are disclosed that monitor and control random cache read operations. Random cache read operation may occur until the expiration of a timer. Upon expiration of the timer, the current random cache read sequence is terminated and new received read commands will not use this sequence. A flash controller may either use a page read operation or initiate a new random cache read sequence.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 13, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Shay Benisty, Tal Sharifie, Yair Baram
  • Patent number: 9891915
    Abstract: A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Mohammad A. Abdallah, Ravishankar Rao
  • Patent number: 9891830
    Abstract: A hierarchal storage management method is provided. The method includes detecting a first portion of a first file being deleted from a hybrid storage device including a hard disk drive (HDD) memory device, a solid state drive (SSD) memory device, and an archival storage memory device. A first set of memory blocks associated with the first portion of the first file is identified. The first set of memory blocks are determined to reside on the SSD memory device. In response, the first set of memory blocks are transferred from the SSD memory device to a first portion of the hybrid storage device.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: February 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Blaine H. Dolph, Nataraj Nagaratnam, Sandeep R. Patil, Riyazahamad M. Shiraguppi
  • Patent number: 9886199
    Abstract: According to one embodiment, a magnetic memory device includes a first memory unit including a first memory array and a first drive unit, a second memory unit including a second memory array and a second drive unit, and a controller. The first memory array includes a first magnetic shift register unit. The second memory array includes a second magnetic shift register unit. The controller subdivides input data into a plurality of one-dimensional bit input arrays. The one-dimensional bit input arrays include a first array and a second array. The controller stores the first array in the first magnetic shift register unit on a last in, first out basis, and stores the second array in the second magnetic shift register unit on a last in, first out basis.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Kondo, Hirofumi Morise, Yasuaki Ootera, Takuya Shimada, Michael Amaud Quinsat, Yoshiaki Osada, Yoshihisa Iwata
  • Patent number: 9886397
    Abstract: A mechanism for simultaneous multithreading is provided. Responsive to performing a store instruction for a given thread of threads on a processor core and responsive to the core having ownership of a cache line in a cache, an entry of the store instruction is placed in a given store queue belonging to the given thread. The entry for the store instruction has a starting memory address and an ending memory address on the cache line. The starting memory addresses through ending memory addresses of load queues of the threads are compared on a byte-per-byte basis against the starting through ending memory address of the store instruction. Responsive to one memory address byte in the starting through ending memory addresses in the load queues overlapping with a memory address byte in the starting through ending memory address of the store instruction, the threads having the one memory address byte is flushed.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: February 6, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi, Martin Recktenwald
  • Patent number: 9886382
    Abstract: Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M Ambroladze, Deanna P Berger, Michael F Fee, Arthur J O'Neill, Robert J Sonnelitter, III
  • Patent number: 9886216
    Abstract: Systems and methods are disclosed for accessing data over a distributed data storage network. A network-attached storage device (NAS) includes a non-volatile memory module comprising a first portion of data storage for storing local user data associated with a host computing device and a second shared portion of data storage for storing third-party data. The NAS includes a controller configured to provide copies of a portion of the user data to one or more other NAS's for storage therein, receive third-party data from each of the one or more other NAS's, and store the received third-party data in the second portion of data storage. The NAS is configured to upload at least a portion of the user data to the host computing device and upload at least a portion of the third-party data to at least one of the one or more other NAS.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: February 6, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventor: Matthew Bennion
  • Patent number: 9880906
    Abstract: Embodiments include methods, apparatus, and systems for managing resources in a physical storage library behind a virtual storage library. In one embodiment, priorities are assigned to copy applications and rules determine which when applications are assigned to resources in the physical storage library.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 30, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Stephen Gold, Shannon Moyes Clark