Patents Examined by Reginald Bragdon
  • Patent number: 9830269
    Abstract: Method and systems for a storage system are provided. Simulated cache blocks of a cache system are tracked using cache metadata while performing a workload having a plurality of storage operations. The cache metadata is segmented, each segment corresponding to a cache size. Predictive statistics are determined for each cache size using a corresponding segment of the cache metadata. The predictive statistics are used to determine an amount of data that is written for each cache size within certain duration. The process then determines if each cache size provides an endurance level after executing a certain number of write operations, where the endurance level indicates a desired life-cycle for each cache size.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: November 28, 2017
    Assignee: NetApp Inc.
    Inventors: Brian D. McKean, Donald R. Humlicek
  • Patent number: 9830268
    Abstract: An arithmetic processing device includes a decoder which decodes commands, a command holding unit configured to register therein the commands involving memory accesses among the decoded commands, a hardware prefetch controller configured to execute a prefetch in response to a trigger independent of a prefetch command to execute the prefetch, the prefetch being an operation of transferring data stored in a memory to a cache memory in advance, and a controller configured to determine whether an unnecessary prefetch command to transfer the data, which is to be transferred to the cache memory by the hardware prefetch controller, from the memory to the cache memory is registered in the command holding unit, and disables the unnecessary prefetch command when the unnecessary prefetch command is registered in the command holding unit.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: November 28, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Shigeru Kimura
  • Patent number: 9832278
    Abstract: A computerized method for dynamic consistency management of server side cache management units in a distributed cache, comprising: updating a server side cache management unit by a client; assigning each of a plurality of server side cache management units to one of a plurality of propagation topology groups according to an analysis of a plurality of cache usage measurements thereof, each of said propagation topology groups is associated with a different write request propagation scheme; and managing client update notifications of members of each of said propagation topology groups according to the respective said different write request propagation scheme which is associated therewith.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Gregory Chockler, Guy Laden, Eli Luboshitz, Roie Melamed, Benjamin M Parees, Yoav Tock
  • Patent number: 9824015
    Abstract: Providing memory management unit (MMU) partitioned translation caches, and related apparatuses, methods, and computer-readable media. In this regard, an apparatus comprising an MMU is provided. The MMU comprises a translation cache providing a plurality of translation cache entries defining address translation mappings. The MMU further comprises a partition descriptor table providing a plurality of partition descriptors defining a corresponding plurality of partitions each comprising one or more translation cache entries of the plurality of translation cache entries. The MMU also comprises a partition translation circuit configured to receive a memory access request from a requestor. The partition translation circuit is further configured to determine a translation cache partition identifier (TCPID) of the memory access request, identify one or more partitions of the plurality of partitions based on the TCPID, and perform the memory access request on a translation cache entry of the one or more partitions.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: November 21, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Edward Podaima, Bohuslav Rychlik, Carlos Javier Moreira, Serag Monier GadelRab, Paul Christopher John Wiercienski, Alexander Miretsky, Kyle John Ernewein
  • Patent number: 9823977
    Abstract: According to certain aspects, a system includes a client device that includes a virtual machine (VM) executed by a hypervisor, a driver located within the hypervisor, and a data agent. The VM may include a virtual hard disk file and a change block bitmap file. The driver may intercept a first write operation generated by the VM to store data in a first sector, determine an identity of the first sector based on the intercepted write operation, determine an entry in the change block bitmap file that corresponds with the first sector, and modify the entry in the change block bitmap file to indicate that data in the first sector has changed. The data agent may generate an incremental backup of the VM based on the change block bitmap file in response to an instruction from a storage manager, where the incremental backup includes the data in the first sector.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 21, 2017
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Henry Wallace Dornemann, Rahul S. Pawar
  • Patent number: 9823840
    Abstract: A storage management system monitors relationships between data sets stored on current implementation resources, such as a storage servers. The relationships may be used to determine whether a data set should be moved from a current implementation resource to an available implementation resource.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: November 21, 2017
    Assignee: Amazon Technologies, Inc.
    Inventors: Marc J. Brooker, David R. Richardson, Tate Andrew Certain, Tobias L. Holgers, Madhuvanesh Parthasarathy
  • Patent number: 9817599
    Abstract: In example implementations, unreferenced memory addresses in a segment of a storage volume may be identified. Access to the segment of the storage volume may be controlled by one of a plurality of storage volume controllers (SVCs). The plurality of SVCs may control access to respective segments of the storage volume. Indicators of the identified unreferenced memory addresses may be stored in a volatile memory in the one of the plurality of SVCs. In response to an input/output (I/O) command from a host, data may be written to one of the identified unreferenced memory addresses corresponding to one of the indicators stored in the volatile memory. After the data has been written, the one of the indicators may be deleted from the volatile memory. The one of the identified unreferenced memory addresses may not have been made available to other SVCs after being identified.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: November 14, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Siamak Nazari, Jin Wang, Srinivasa D Murthy
  • Patent number: 9817762
    Abstract: The disclosed embodiments relate to a computing system that facilitates performing prefetching for scatter/gather operations. During operation, the system receives a scatter/gather prefetch instruction at a processor core, wherein the scatter/gather prefetch instruction specifies a virtual base address, and a plurality of offsets. Next, the system performs a lookup in a translation-lookaside buffer (TLB) using the virtual base address to obtain a physical base address that identifies a physical page for the base address. The system then sends the physical base address and the plurality of offsets to a cache. This enables the cache to perform prefetching operations for the scatter/gather instruction by adding the physical base address to the plurality of offsets to produce a plurality of physical addresses, and then prefetching cache lines for the plurality of physical addresses into the cache.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: November 14, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Sanjiv Kapil, Darryl J. Gove
  • Patent number: 9817760
    Abstract: The disclosure relates to filtering snoops in coherent multiprocessor systems. For example, in response to a request to update a target memory location at a Level-2 (L2) cache shared among multiple local processing units each having a Level-1 (L1) cache, a lookup based on the target memory location may be performed in a snoop filter that tracks entries in the L1 caches. If the lookup misses the snoop filter and the snoop filter lacks space to store a new entry, a victim entry to evict from the snoop filter may be selected and a request to invalidate every cache line that maps to the victim entry may be sent to at least one of the processing units with one or more cache lines that map to the victim entry. The victim entry may then be replaced in the snoop filter with the new entry corresponding to the target memory location.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 14, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Eric Francis Robinson, Khary Jason Alexander, Zeid Hartuon Samoail, Benjamin Charles Michelson
  • Patent number: 9817763
    Abstract: A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory comprising a plurality of NVM lines.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Alistair Robertson, Nancy Amedeo, Mark Maiolani
  • Patent number: 9817583
    Abstract: An information processing device includes a processor. The processor is configured to allocate a plurality of allocation unit areas to a virtual volume from a first storage device and a second storage device. The processor is configured to generate evaluation information related to access for each of a plurality of divided areas into which each of the plurality of allocation unit areas is divided. The processor is configured to determine based on the generated evaluation information, when allocation to the virtual volume is changed from a first allocation unit area of the first storage device to a second allocation unit area of the second storage device, a first data transfer order of transferring data in divided area units from the first allocation unit area to the second allocation unit area. The processor is configured to transfer the data in accordance with the first data transfer order.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: November 14, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Kazutaka Ogihara, Kazuichi Oe, Motoyuki Kawaba
  • Patent number: 9817769
    Abstract: In one embodiment, a method includes receive a translation vector, selecting a translation entry from a plurality of translation entries, and determining whether the translation entry is associated with a first identifier class or a second identifier class. The translation vector includes a first identifier, a second identifier, and a virtual memory identifier. The first identifier is associated with a first identifier class, and the second identifier is associated with a second identifier class. The translation vector is received from a translation module including a memory configured to store the plurality of translation entries. Each translation entry from the plurality of translation entries including a virtual memory identifier. The translation entry is selected from the plurality of translation entries of the translation module based on the virtual memory identifier of the translation vector.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: November 14, 2017
    Assignee: Juniper Networks, Inc.
    Inventors: Xiangwen Xu, Hexin Wang, Xiang Zhu
  • Patent number: 9811262
    Abstract: Accesses to a number of data blocks stored in a distributed storage are observed. Following observation of the accesses, the stored data blocks are redistributed. In one aspect, redistribution of the data blocks includes determining the access patterns for one or more of the data blocks based on the observed accesses, and determining the storage sizes for the one or more data blocks. Thereafter, based on the determined access patterns and determined storage sizes, the one or more data blocks are sorted. Subsequently, the one or more data blocks are redistributed or rebalanced across a number of storage devices of the distributed storage based on the sorting. In one aspect, the one or more data blocks are redistributed according to either a uniform distribution scheme or a proportional distribution scheme.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 7, 2017
    Inventors: Silvius V. Rus, Michael Ovsiannikov
  • Patent number: 9811472
    Abstract: Embodiments relate to managing memory page tables in a processing system. A request to access a desired block of memory is received. The request includes an effective address that includes an effective segment identifier (ESID) and a linear address, the linear address including a most significant portion and a byte index. An entry in a buffer that includes the ESID of the effective address is located. Based on the entry including a radix page table pointer (RPTP), performing: using the RPTP to locate a translation table of a hierarchy of translation tables, using the located translation table to translate the most significant portion of the linear address to obtain an address of a block of memory, and based on the obtained address, performing the requested access to the desired block of memory.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: November 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Bybell, Michael K. Gschwind
  • Patent number: 9811456
    Abstract: In one form, a data processor comprises a memory accessing agent and a memory controller. The memory accessing agent selectively initiates read accesses to and write accesses from a memory. The memory controller is coupled to the memory accessing agent and is adapted to be coupled to the memory and to access the memory using a start-gap wear-leveling algorithm. The memory controller is adapted to maintain a metadata log in a region of the memory and to store in the metadata log a start address and a gap address used in the start-gap wear-leveling algorithm, and upon initialization to access the metadata log to retrieve an initial start address and an initial gap address for use in the start-gap wear-leveling algorithm. In another form, a memory module may comprise a memory buffer including such a memory controller.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: November 7, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David A. Roberts
  • Patent number: 9811422
    Abstract: Head start population of an image backup. In one example embodiment, a method for head start population of an image backup may include tracking blocks that are modified in a source storage between a first point in time and a second point in time, head start copying a first portion of the modified blocks into the image backup prior to the second point in time, activating a snapshot on the source storage at the second point in time where the snapshot represents a state of the source storage at the second point in time, and copying, subsequent to the second point in time, from the snapshot and into the image backup, a second portion of the modified blocks that were not yet copied into the image backup by the second point in time.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: November 7, 2017
    Assignee: STORAGECRAFT TECHNOLOGY CORPORATION
    Inventor: Nathan S. Bushman
  • Patent number: 9812186
    Abstract: A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 7, 2017
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuan Ruan, Mingyu Chen
  • Patent number: 9811551
    Abstract: A system and method for managing fingerprint tables in deduplicating storage systems. A computer system includes a storage device and a data storage controller coupled to the storage device. The controller is configured to for each of a plurality of data objects stored in a storage device, determine, based on one or more attributes corresponding to usage of the data object, a probability of the data object being deduplicated; store within a first fingerprint table, fingerprints of data objects with the highest probability of being deduplicated; store within a second fingerprint table, fingerprints of data objects with a lower probability of being deduplicated than the data objects having fingerprints stored in the first fingerprint table; and search fingerprints of the first fingerprint table to determine whether a fingerprint for a data object associated with a write request matches a fingerprint for any of the data objects in the first fingerprint table.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: November 7, 2017
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, John Hayes, Ethan Miller, Joseph S. Hasbani, Cary Sandvig
  • Patent number: 9804970
    Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 31, 2017
    Assignee: International Business Machines Corporation
    Inventors: Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck
  • Patent number: 9804972
    Abstract: Activation rates of memory locations associated with memory addresses are monitored. The activation rates of the memory locations associated with the memory addresses are regulated. The regulating of the activation rates of the memory locations associated with the memory addresses includes selectively updating a cache with the memory addresses based on the activation rates.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: October 31, 2017
    Assignee: Hewlett-Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, William James Walker, Andrew C. Walton