Patents Examined by Richard Elms
  • Patent number: 10381081
    Abstract: A memory device includes first and second electrode layers, first and second semiconductor pillars, an interconnect, and a first connecting conductor. The first and second electrode layers are stacked in a first direction. The second electrode layers are positioned in the first direction when viewed from the first electrode layers. The first semiconductor pillar extends in the first direction through the first electrode layers. The second semiconductor pillar extends in the first direction through the second electrode layers. The interconnect is provided between the first and second electrode layers, and is electrically connected to the first and second semiconductor pillars. The first connecting conductor extends in the first direction, is connected to one of the first electrode layers and one of the second electrode layers. The first connecting conductor extends in the first direction, and crosses at least one of the second electrode layers.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 13, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Tsuyoshi Sugisaki, Yasuhito Nakajima
  • Patent number: 10354030
    Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 10198211
    Abstract: A hybrid memory system may include: a volatile memory; a nonvolatile memory; and a memory controller configured to a threshold value for a read-to-write ratio according to a refresh interval of the volatile memory, and to perform migration of a page between the volatile memory and the nonvolatile memory based on the threshold value and a read-to-write ratio of the page.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: February 5, 2019
    Assignees: SK HYNIX INC., KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Sung Woo Chung, Young Ho Gong, Jae Hoon Chung, Hoon Hee Cho
  • Patent number: 10176876
    Abstract: A memory control method includes providing a memory including a first area and a second area, and reading data in the first area and the second area when receiving data to be stored. The method also includes selecting, from the first area and the second area, an area in which the data is in an erased state. In addition, the method includes performing a programming operation on each memory cell in the selected area to write the data to be stored into the selected area. Further, the method includes—performing an erase operation on a remaining area in the first area and the second area to perform a next data writing process, after writing the data to be stored into the selected area.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: January 8, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Shi Cong Zhou
  • Patent number: 10141045
    Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: November 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chiting Cheng, Yangsyu Lin
  • Patent number: 10127993
    Abstract: One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: November 13, 2018
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Steve S. Chung, E-Ray Hsieh, Zhi-Hong Huang
  • Patent number: 10127964
    Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: November 13, 2018
    Assignee: Yale University
    Inventors: Xiao Sun, Tso-Ping Ma
  • Patent number: 10095568
    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: October 9, 2018
    Assignee: Seagate Technology LLC
    Inventors: Antoine Khoueir, Stacey Secatch, Kevin Gomez, Ryan Goss
  • Patent number: 10090055
    Abstract: Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.
    Type: Grant
    Filed: March 22, 2017
    Date of Patent: October 2, 2018
    Assignee: SK Hynix Inc.
    Inventor: Tae Heui Kwon
  • Patent number: 10074411
    Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: September 11, 2018
    Assignee: Nvidia Corporation
    Inventors: Daehyun Chung, Sunil Sudhakaran
  • Patent number: 10062438
    Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: August 28, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Sukegawa, Ikuo Magaki, Tokumasa Hara, Shirou Fujita
  • Patent number: 10056146
    Abstract: The system includes a data storage medium comprising cells, an excitation circuit, and an emitter. The cells arranged in a three dimensional space. The excitation circuit excites each cell independently. Exciting a cell changes an optical property of the cell. The emitter emits a first beam onto a first cell during a first excitation period to orient electrical charges within the first cell to a first oriented value and intensity of electric field to a first intensity value. The emitter emits a second beam onto a second cell during a second excitation period to orient electrical charges within the second cell to a second oriented value and intensity of electric field to a second intensity value. The first and second cells maintain the first and the second oriented values and the first and second intensity values after the first and second excitation periods are over, respectively.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: August 21, 2018
    Assignee: Seagate Technology LLC
    Inventors: Joachim Ahner, David Marcus Tung
  • Patent number: 10056142
    Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: August 21, 2018
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Ning Ge, Jianhua Yang, Zhiyong Li, R. Stanley Williams
  • Patent number: 10042702
    Abstract: A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: August 7, 2018
    Assignee: SK Hynix Inc.
    Inventor: Sang-Jin Byeon
  • Patent number: 10042588
    Abstract: Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: August 7, 2018
    Assignee: SK hynix Inc.
    Inventor: Jae-Yong Kang
  • Patent number: 10037244
    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Ho-Young Song, Hyun-Joong Kim
  • Patent number: 10026456
    Abstract: Write-assist circuits for memory bit cells (“bit cells”) employing a P-type Field-Effect transistor (PFET) write port(s) are disclosed. Related methods and systems are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-Effect transistor (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide bit cells having PFET write ports, as opposed to NFET write ports, to reduce memory write times to the bit cells, and thus improve memory performance. To mitigate a write contention that could otherwise occur when writing data to bit cells, a write-assist circuit provided in the form of positive bitline boost circuit can be employed to strengthen a PFET access transistor in a memory bit cell having a PFET write port(s).
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: July 17, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Jihoon Jeong, Francois Ibrahim Atallah, Keith Alan Bowman, David Joseph Winston Hansquine, Hoan Huu Nguyen
  • Patent number: 10026484
    Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: July 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Noboru Shibata
  • Patent number: 10020039
    Abstract: A magnetoresistive device includes a magnetic free layer having first and second surfaces, the magnetic free layer being comprised of a ferromagnetic material having a perpendicular magnetic anisotropy, a spin current generation layer contacting the first surface of the magnetic free layer, a tunnel barrier layer having one surface contacting the second surface of the magnetic free layer, a reference layer contacting another surface of the tunnel barrier layer, and a leakage field generation layer including first and second leakage field generation layers each of which is comprised of a ferromagnetic material and generates a leakage field, an in-plane component of the leakage field at an part of the magnetic free layer is formed generating a domain wall having an in-plane magnetization component in the magnetic free layer.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 10, 2018
    Assignee: TOHOKU UNIVERSITY
    Inventors: Shunsuke Fukami, Michihiko Yamanouchi, Hideo Ohno
  • Patent number: 9997237
    Abstract: A memory including an array of nvRAM cells and method of operating the same, where each nvRAM cell includes a volatile charge storage circuit, and a nonvolatile charge storage circuit including a solitary non-volatile memory (NVM) device, a first transistor coupled to the NVM device through which data is coupled to the volatile charge storage circuit, a second transistor coupled to the NVM device through which a compliment of the data is coupled to the volatile charge storage circuit and a third transistor through which the NVM device is coupled to a positive voltage supply line (VCCT). In one embodiment, the first transistor is coupled to a first node of the NVM device, the second transistor is coupled to a second node of the NVM device and the third transistor is coupled between the first node and VCCT. Other embodiments are also disclosed.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 12, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Joseph S Tandingan, David W. Still, Jesse J Siman, Jayant Ashokkumar