Abstract: The present disclosure discloses a feedback field-effect electronic device using a feedback loop operation and an array circuit using the feedback field-effect electronic device. According to one embodiment of the present disclosure, the array circuit includes a plurality of feedback field-effect electronic devices in which the source region of a diode structure and the drain region of an access electronic device are connected in series, wherein the diode structure is connected to a bit line and a first word line, the access electronic device is connected to a source line and a second word line, and a random access operation is performed by selectively applying voltage to the bit line and the first and second word lines.

Abstract: A solid state drive (SSD) device includes a first nonvolatile memory package, a second nonvolatile memory package, and a controller. The first nonvolatile memory package includes a first buffer chip and a plurality of first nonvolatile memory chips. The second nonvolatile memory package includes a plurality of second nonvolatile memory chips. The controller controls the first nonvolatile memory package and the second nonvolatile memory package. The first buffer chip communicates a first address signal and a first data with the controller, and selectively communicates the first data with one of the plurality of first nonvolatile memory chips and the plurality of second nonvolatile memory chips based on the first address signal.

Abstract: A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a semiconductor pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a conductive region formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.

Abstract: Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract: A memory device includes first and second electrode layers, first and second semiconductor pillars, an interconnect, and a first connecting conductor. The first and second electrode layers are stacked in a first direction. The second electrode layers are positioned in the first direction when viewed from the first electrode layers. The first semiconductor pillar extends in the first direction through the first electrode layers. The second semiconductor pillar extends in the first direction through the second electrode layers. The interconnect is provided between the first and second electrode layers, and is electrically connected to the first and second semiconductor pillars. The first connecting conductor extends in the first direction, is connected to one of the first electrode layers and one of the second electrode layers. The first connecting conductor extends in the first direction, and crosses at least one of the second electrode layers.

Abstract: Apparatuses and methods for measuring an electrical characteristic of a model signal line and providing measurement information based at least in part on the measurement of the electrical characteristic. An example apparatus includes a signal line model including a model signal line configured to model electrical characteristics of a signal line. The apparatus further includes a measurement circuit coupled to the signal line model and configured to measure the electrical characteristic of the model signal line responsive to an input signal provided to the model signal line. The measurement circuit is further configured to provide measurement information based at least in part on the measurement to set a signal applied to the signal line.

Abstract: A hybrid memory system may include: a volatile memory; a nonvolatile memory; and a memory controller configured to a threshold value for a read-to-write ratio according to a refresh interval of the volatile memory, and to perform migration of a page between the volatile memory and the nonvolatile memory based on the threshold value and a read-to-write ratio of the page.

Abstract: A memory control method includes providing a memory including a first area and a second area, and reading data in the first area and the second area when receiving data to be stored. The method also includes selecting, from the first area and the second area, an area in which the data is in an erased state. In addition, the method includes performing a programming operation on each memory cell in the selected area to write the data to be stored into the selected area. Further, the method includes—performing an erase operation on a remaining area in the first area and the second area to perform a next data writing process, after writing the data to be stored into the selected area.

Abstract: A dual rail device includes a first power domain circuit coupled to a first power supply through a first header control switch and a second power domain circuit coupled to a second power supply. The first and second power supplies have different steady-state voltage levels. The first power domain circuit is interfaced to the second power domain circuit. The device also includes a power detector circuit for providing a control signal for the first header control switch responsive to a voltage level of the second power supply.

Abstract: Exemplary embodiments of the present disclosure are directed to circuitry for effective operation of Ferroelectric-gated FET (FeFET) memories. Exemplary embodiment of the present disclosure includes circuits and/or circuit blocks to facilitate memory refresh, error checking and correcting (ECC), reading and sensing memory cells, program and erase operations, and other control and periphery operations for FeFET memory cell arrays.

Abstract: One time programming and repeatably random read integrated circuit memory has a storage device that programs the information by using dielectric-fuse mechanism. The main characteristics of dielectric fuse mechanisms is that by applying an electric field on the dielectrics, the ions or atoms in the dielectrics are drifted-out, or the dielectrics are burned-out, that create damage of the dielectric structure in a form of porosity, and the conductivity (resistivity) of tunneling current through the dielectrics changes the state from high conductivity (resistivity) to low conductivity (resistivity). The dielectric fuse mechanism has been integrated in VLSI circuits, completed the validation, and implemented by the fabrication of CMOS process.

Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

Abstract: Provided herein is a voltage generating circuit including: a negative voltage pump configured to generate a first negative voltage; and a negative voltage regulator configured to generate a second negative voltage using the first negative voltage and output the second negative voltage through an output terminal. The negative voltage regulator includes a first amplifier circuit configured to be controlled by a voltage of the output terminal, and a voltage booster configured to increase a voltage of the output terminal depending on an output voltage of the first amplifier circuit.

Abstract: A memory driver, a method of driving a command bus for a synchronous dual data rate (sDDR) memory and a memory controller for controlling dynamic random-access memory (DRAM). In one embodiment, the memory driver includes: (1) pull-up and pull-down transistors couplable to a command bus of a memory controller and operable in 1N and 2N timing modes and (2) gear down offset circuitry coupled to the pull-up transistor and operable to offset the command bus when transitioning out of the 1N timing mode and increase an extent and duration of 1-0-1 transitions on the command bus.

Abstract: A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Abstract: The system includes a data storage medium comprising cells, an excitation circuit, and an emitter. The cells arranged in a three dimensional space. The excitation circuit excites each cell independently. Exciting a cell changes an optical property of the cell. The emitter emits a first beam onto a first cell during a first excitation period to orient electrical charges within the first cell to a first oriented value and intensity of electric field to a first intensity value. The emitter emits a second beam onto a second cell during a second excitation period to orient electrical charges within the second cell to a second oriented value and intensity of electric field to a second intensity value. The first and second cells maintain the first and the second oriented values and the first and second intensity values after the first and second excitation periods are over, respectively.

Abstract: A device for generating a representative logic indicator of grouped memristors is described. The device includes a memristor array. The memristor array includes a number of first memristors having a first set of logic indicators and a number of second memristors having a second set of logic indicators. The second set of logic indicators is different than the first set of logic indicators. Each first memristor is grouped with a corresponding second memristor during a memory read operation to generate a representative logic indicator.

Abstract: A semiconductor package includes: memory devices that are stacked one on another; and an inter-layer channel for communication between the memory devices, wherein each memory device includes: a data pad; a memory core; a data input/output circuit that inputs/outputs data through the data pad; an inter-layer channel transfer circuit that transfers a read data transferred from the memory core to the inter-layer channel or transfers a data inputted through the data input/output circuit to the inter-layer channel; an inter-layer channel reception circuit receiving the data of the inter-layer channel; a read error correction circuit correcting an error of the data transferred from the inter-layer channel reception circuit to produce an error-corrected data and transfers the error-corrected data to the data input/output circuit; and a write error correction circuit generating a parity data to be stored in the memory core based on the data transferred from the inter-layer channel reception circuit.

Abstract: Disclosed is an operating method of an electronic device which includes a semiconductor memory having a plurality of resistive storage cells. The operating method may include: writing data to the resistive storage cells using a write current of a set condition; determining whether the writing of data to the resistive storage cells is successful, wherein the writing of data is determined to be failed when the number of resistive storage cells with failed writing of data exceeds a reference value, and successful when the number of resistive storage cells with failed writing of data is equal to or less than the reference value; strengthening the set condition when the writing of data is determined to be failed; and easing the set condition when the writing of data is determined to be successful.