Patents Examined by Richard Elms
  • Patent number: 9916882
    Abstract: A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: March 13, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Satoshi Shirotori, Hiroaki Yoda, Yuichi Ohsawa, Yuuzo Kamiguchi, Naoharu Shimomura, Tadaomi Daibou, Tomoaki Inokuchi
  • Patent number: 9911472
    Abstract: Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver circuit receives complementary global write bitline signals as input signals from a global write bitline driver in the low voltage domain, and a write enable signal as an input signal in the high voltage domain. The write bitline driver circuit generates complementary local write bitline signals as output signals in the high voltage domain for activating bitlines of a memory bank in the high voltage domain. The complementary local write bitline signals are based on the complementary global write bitline signals, voltage level shifted from the low voltage domain to the high voltage domain and gated by the write enable signal.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: March 6, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shaoping Ge, Chiaming Chai, Stephen Edward Liles, Manish Garg
  • Patent number: 9899067
    Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: John S. Bialas, Jr., David D. Cadigan, Stephen P. Glancy, Warren E. Maule, Gary A. Van Huben
  • Patent number: 9898194
    Abstract: An object is to solve all of the following problems caused when a volatile register and a non-volatile register are used as registers in a processor: degradation of the integrity of data stored in the non-volatile register; loss of data security due to the processor and a non-volatile memory device that are provided apart from each other; and slow data processing speed due to wiring delay or the like caused by these devices provided apart from each other. When data maintained in the volatile register is stored in the non-volatile register before supply of power supply voltage is stopped, the data is encrypted by an encryption circuit and stored in a non-volatile memory device that is provided separately from the processor. Then, the data stored in the non-volatile register is compared with the compressed and encrypted data stored in the non-volatile memory device.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: February 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Tomoaki Atsumi, Masaaki Hiroki
  • Patent number: 9892800
    Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: February 13, 2018
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Eli Harari
  • Patent number: 9892764
    Abstract: A semiconductor chip includes a first circuit block configured to receive a first power supply voltage through a first power supply terminal of the semiconductor chip, a second circuit block configured to receive a second power supply voltage through a second power supply terminal of the semiconductor chip, and an alternative supply unit that is connected between the first power supply terminal and the first circuit block and receives the first power supply voltage through the first power supply terminal. The alternative supply circuit is configured to apply an alternative power supply voltage generated using the second power supply voltage to the first circuit block in response to a supply of the first power supply voltage being stopped.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Il Kim
  • Patent number: 9887009
    Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: February 6, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chung-Kuang Chen, Han-Sung Chen, Chung-Hsiung Hung
  • Patent number: 9875035
    Abstract: A memory device includes: a memory including a plurality of blocks, each including a plurality of pages; and a control logic that controls a read operation and a copy-back operation on the memory based on a combination of a block read operation number and a page read operation number.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: January 23, 2018
    Assignee: SK Hynix Inc.
    Inventor: Beom-Ju Shin
  • Patent number: 9875804
    Abstract: A nonvolatile semiconductor memory device includes a memory cell array. The memory cells of the memory cell array can be programmed to have different threshold voltages. A word line is connected to the memory cells. A controller is configured to receive a first command and perform a first read sequence and a second read sequence to read data from the memory cell array. In the first read sequence, a series of different voltage levels are applied to the word line and data is read from the array at each voltage level. In the second read sequence, a read voltage level is set based on the data obtained during the first read sequence. The read voltage level is applied to the word line to read the data to be output from the memory cell array.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: January 23, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Naoya Tokiwa
  • Patent number: 9865336
    Abstract: A semiconductor memory includes a first data line, a second data line, a first coupling line, a second coupling line, a first plurality of transistors, and a second plurality of transistors. The first coupling line is configured to be capacitively coupled with the first data line. The second coupling line is configured to be capacitively coupled with the second data line. The first plurality of transistors are configured to transmit a first voltage to the first coupling line and the second coupling line in response to a first control signal. The second plurality of transistors are configured to transmit a second voltage to the first coupling line, the second coupling line, or a combination thereof in response to a second control signal and a third control signal.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 9865314
    Abstract: An operation instruction generating circuit and a consumable chip. The operation instruction generating circuit includes: a power-on initialization module, connected to a signal wire and used for generating an initialization signal according to a signal transmitted by the signal wire; a middle signal generating module, connected to the power-on initialization module and the signal wire and used for combining, according to the initialization signal, the signal transmitted by the signal wire to generate a middle signal; and an instruction generating module, connected to the power-on initialization module and the middle signal generating module and used for generating an operation instruction according to the initialization signal and the middle signal or according to the initialization signal, the middle signal, and the signal transmitted by the signal wire. By the operation instruction generating circuit, the consumable chip is enabled to accurately respond to actions of a printing imaging device in time.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 9, 2018
    Assignee: APEX MICROELECTRONICS CO., LTD.
    Inventors: Wanli Sun, Xiongwei Wang, Ruyan Xue, Huiling Yang
  • Patent number: 9865318
    Abstract: A transmission circuit may be provided. The transmission circuit may include a strobe control circuit and an output driver. The strobe control circuit may generate strobe driving signals based on information and a clock signal. The output driver may generate a strobe signal by driving a signal transmission line. The transmission circuit may drive the signal transmission line to a specified level for a predetermined time after transmission of the strobe signal is completed.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventors: Kyung Hoon Kim, Sun Ki Cho
  • Patent number: 9865338
    Abstract: A controller executes a first data conversion for write data to be written into a first page. The first data conversion includes increasing a ratio of a number of a first value to a total number of pieces of data. The controller executes a second data conversion for write data to be written into a second page. The second data conversion includes increasing a ratio of the number of the second value to the total number of pieces of data.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: January 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tokumasa Hara, Kiichi Tachi, Susumu Tamon, Shigefumi Irieda
  • Patent number: 9858985
    Abstract: An SRAM cell includes first and second inverters which are cross-coupled to one another to establish first and second data storage nodes, which are complementary. A first access transistor includes a first source/drain region coupled to the first data storage node, a first drain/source region coupled to a first bitline, and a first gate region coupled to a wordline. A second access transistor includes a second source/drain region coupled to the second complementary data storage node, a second drain/source region coupled to a second bitline, and a second gate region coupled to the wordline. A first dummy transistor has a first dummy source/drain region coupled to the first source/drain region of the first access transistor. A second dummy transistor has a second dummy source/drain region coupled to the second source/drain region of the second access transistor.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Patent number: 9851899
    Abstract: A nonvolatile memory device includes a multi-level cell which stores M-bit data at a time and M number of latches for respectively storing M-bit data on a single bit basis. A controller sequentially latches M-bit data of the multi-level cell into the M number of latches, respectively, during a first half read period, and sequentially outputs the latched M-bit data in the M number of latches during a second half read period.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: December 26, 2017
    Assignee: SK Hynix Inc.
    Inventor: Byoung-Sung You
  • Patent number: 9847133
    Abstract: A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory cells, and each memory cell includes a floating gate module, a control element, and an erase element. Memory bytes of the same column are coupled to the same erase line, and memory bytes of different columns are coupled to different erase lines. Therefore, the memory array is able to support byte operations while the memory cells of the same memory byte can share the same wells. The circuit area of the memory array can be reduced and the operation of the memory array can be more flexible.
    Type: Grant
    Filed: May 10, 2016
    Date of Patent: December 19, 2017
    Assignee: eMemory Technology Inc.
    Inventors: Tsung-Mu Lai, Chih-Hsin Chen, Shih-Chen Wang, Chen-Hao Po
  • Patent number: 9842035
    Abstract: A semiconductor system includes one or more core chips including a plurality of memory banks; one or more replacement storage units; and a base chip suitable for: first detecting a memory bank having an access frequency that satisfies a first condition, second detecting whether an utilization rate of the first detected memory bank satisfies a second condition, and replacing the second detected memory bank with one among the replacement storage units.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: December 12, 2017
    Assignee: SK Hynix Inc.
    Inventors: Kyung-Min Lee, Young-Ook Song, Ki-Joong Kim, Yong-Ju Kim, Jung-Hyun Kwon, Sang-Gu Jo
  • Patent number: 9842649
    Abstract: Apparatus and methods are disclosed, including a method that performs a first operation on a first resistance variable element using a common source voltage, a first data line voltage and a first control gate voltage, and then performs a second operation on a second resistance variable element using the common source voltage, a second data line voltage and a second control gate voltage. Additional apparatus and methods are described.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: December 12, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Seshadri K. Kolluri, Rajesh N. Gupta
  • Patent number: 9842659
    Abstract: Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.
    Type: Grant
    Filed: February 6, 2015
    Date of Patent: December 12, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-wan Nam, Byung-gil Jeon, Dae-seok Byeon
  • Patent number: 9837162
    Abstract: A semiconductor device that can rapidly stabilize a control voltage for controlling an electric current source is provided. A semiconductor device includes a filter circuit that is provided between a control voltage generation circuit and an electric current source and removes noise of the control voltage. The filter circuit includes a first resistive element that is provided between the control voltage generation circuit and an output node that outputs the control voltage, a first capacitive element that is provided between the output node and a first voltage, a second capacitive element that is coupled between the output node and the first voltage via a first switch element. The second capacitive element is coupled between the first voltage and a second voltage when the first switch element is non-conductive. The second capacitive element is coupled with the first capacitive element through the output node when the first switch element is conductive.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Kawae, Takafumi Noguchi, Atsuo Yoneyama