Patents Examined by Richard Elms
  • Nonvolatile memory module having backup function
    Patent number: 9824734
    Abstract: Disclosed is a memory system. The memory system includes a volatile memory device configured to exchange data with a host through a first channel, a nonvolatile memory device, and a memory controller connected with the volatile memory device through a second channel. The memory controller detects a request of the host or a power state and controls the volatile memory device and the nonvolatile memory device based on the detection result such that data stored in the volatile memory device is backed up in the nonvolatile memory device through the second channel. The volatile memory device includes a first interface for communicating with the host through the first channel and a second interface for communicating with the memory controller through the second channel.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngjin Cho, Younggeun Lee, Han-Ju Lee, Hyo-Deok Shin
  • Memory device and operating method thereof
    Patent number: 9818491
    Abstract: A memory device includes a plurality of memory cells for storing data; a plurality of memory cells for storing data; a non-volatile memory unit; a test control unit suitable for detecting weak memory cells among the plurality of memory cells; a program control unit suitable for controlling addresses of the detected weak memory cells to be programmed in the non-volatile memory unit; and a refresh control unit suitable for refreshing the addresses stored in the non-volatile memory unit more frequently than other memory cells.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: November 14, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jong-Sam Kim, Jae-Il Kim
  • Non-volatile memory with intelligent temperature sensing and local throttling
    Patent number: 9811267
    Abstract: A non-volatile storage apparatus comprises a controller, one or more memory packages, a system temperature sensor, and one or more memory temperature sensors. The system temperature sensor is located at or on the controller. Each of the one or more memory temperature sensors are positioned at one of the one or more memory packages. The controller monitors system temperature using the system temperature sensor. If the system temperature is above a first threshold, then temperature is sensed at the memory packages using the one or more memory temperature sensors. Individual memory packages have their performance throttled if their temperature exceeds a second threshold.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: November 7, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Nian Niles Yang, Grishma Shah, Phil Reusswig, Dmitry Vaysman
  • Nonvolatile memory device, operating method thereof, and test system for optimizing erase loop operations
    Patent number: 9786374
    Abstract: A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: October 10, 2017
    Assignee: SK hynix Inc.
    Inventor: Jae Won Cha
  • Operation aware auto-feedback SRAM
    Patent number: 9767890
    Abstract: A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a write operation. The SRAM cell includes a first pass gate and a second pass gate. A first resistor is coupled between the first pass gate and a first side of the storage cell. A second resistor is coupled between the second pass gate and a second side of the storage cell.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: September 19, 2017
    Assignee: Intel Corporation
    Inventors: Pramod Kolar, Eric A. Karl
  • Capacitive sensing and reference voltage scheme for random access memory
    Patent number: 9767875
    Abstract: A method uses a memory that includes a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. The output of the amplifier is coupled to the inverting input of the amplifier while the non-inverting input receives the reference. The output is decoupled from the inverting input to store a voltage on the inverting input of the amplifier. A non-volatile (NV) element of a first NVM cell of the plurality of NVM cells is coupled to the non-inverting input. An output signal representative of the state of the NVM cell is provided.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: September 19, 2017
    Assignee: NXP USA, Inc.
    Inventors: Anirban Roy, Thomas Jew
  • Static random access memory cell and manufacturing method thereof
    Patent number: 9761302
    Abstract: A SRAM cell includes a first pass-gate device and a second-pass gate device comprising a first conductivity type, a first pull-down device and a second pull-down device comprising the first conductivity type, and a first pull-up device and a second pull-up device comprising a second conductivity type complementary to the first conductivity type. The first pass-gate device and the second pass-gate device respectively include first lightly-doped drains (hereinafter abbreviated as LDDs. The first pull-down device and the second pull-down device respectively include second LDDs. And a dosage of the first LDDs is different from a dosage of the second LDDs.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: September 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tien-Yu Lu, Chang-Hung Chen, Chun-Hsien Huang, Han-Tsun Wang, Jheng-Tai Yan, Yu-Tse Kuo
  • Refresh circuitry
    Patent number: 9741421
    Abstract: The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: August 22, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Richard N. Hedden
  • Overvoltage protection for a fine grained negative wordline scheme
    Patent number: 9734892
    Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Pilo, Richard S. Wu
  • Overvoltage protection for a fine grained negative wordline scheme
    Patent number: 9734891
    Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: August 15, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Harold Pilo, Richard S. Wu
  • Method and device for iteratively updating read voltages
    Patent number: 9728263
    Abstract: A data storage device includes a memory and a controller. Read voltages are updated based on adjusting a first read voltage without adjusting a second read voltage to generate multiple sets of read voltages, and the multiple sets of read voltages are used to generate multiple representations of data. A value of the first read voltages is selected based on error correction coding (ECC) related information related to the multiple representations of the data. In another embodiment, storage elements of the memory are sensed using a set of candidate read voltages to generate sensing data that is transferred to a memory accessible to the controller. The multiple representations of data may be generated based on the sensing data to emulate results of reading the storage elements using a different combination of candidate reading voltages.
    Type: Grant
    Filed: August 14, 2013
    Date of Patent: August 8, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Eran Sharon, Evgeny Mekhanik, Idan Alrod
  • Memory device
    Patent number: 9728268
    Abstract: According to one embodiment, a memory device includes a controller, and a nonvolatile memory controlled by the controller, the nonvolatile memory executing an erase operation by an algorithm which repeats loops, each loop including an erase step applying an erase pulse to a memory cell and a verify step verifying a threshold voltage of the memory cell after the erase step, an erase-verify-read voltage using the verify step changing in a x-th loop (x is a natural number equal to or larger than 2). The controller is capable of changing a value of x, and indicates the value of x to the nonvolatile memory.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazutaka Takizawa, Masaaki Niijima
  • Automatic built-in self test for memory arrays
    Patent number: 9715944
    Abstract: A memory array includes m·(n+1) memory cells, wherein n and m are natural numbers greater than zero. Each of the plurality of memory cells is connected to one of (n+1) bitlines and one of m wordlines. The memory array further includes n outputs configured for reading a content of the memory array. The memory array further includes n output switches, wherein an i-th output switch is configured for selectively connecting, in response to a switching signal, either an i-th bitline or an (i+1)-th bitline to an i-th output, and wherein i is a natural number and 0?i?n?1. The memory array further includes an (n+1)-th output switch, wherein the (n+1)-th output switch is configured for selectively connecting, in response to the switching signal, either the (n+1)-th bitline or a defined potential to an (n+1)-th output.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: July 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Lior Binyamini, Stefan Payer, Wolfgang Penth, Ido Rozenberg
  • ROM segmented bitline circuit
    Patent number: 9704874
    Abstract: A bitline structure for use in a memory device may be connected to a plurality of bit memory cells. The bitline may be segmented into segments connected to one-third of the plurality of bit memory cells and two-thirds of the bit memory cells, respectively. The segments may be electrically coupled to each other to provide an overall bitline output.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: July 11, 2017
    Assignee: eASIC Corporation
    Inventors: Ban P. Wong, Hui Hui Ngu
  • Self-stuffing multi-clock FIFO requiring no synchronizers
    Patent number: 9703526
    Abstract: An asynchronous first in first out memory device eliminates the need for synchronizers. The device includes pipeline of data registers. The data registers include a first register to accept data writes of data and a last register data reads. Each register has an enable input to indicate a full condition allowing a read and an empty condition allowing a write. A bubble inserter circuit inserts a bubble in the first register to prevent a completely empty condition for all registers. Controllers are associated with each register to allow the bubble or written data to be passed from the first register to the last register. A near empty detect circuit is coupled to the registers to determine a nearly empty condition of the pipeline. An arbiter determines whether a data write proceeds or a bubble insertion proceeds for the first register when the plurality of registers is near empty.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: July 11, 2017
    Assignee: Altera Corporation
    Inventor: Dana How
  • Semiconductor storage device and test method thereof using a common bit line
    Patent number: 9697911
    Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: July 4, 2017
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Adaptive operation of 3D memory
    Patent number: 9691473
    Abstract: A three dimensional nonvolatile memory system includes a sensing unit configured to sense bit line current and/or voltage for bit lines of a plurality of separately-selectable portions of a block and to compare respective results with a reference and an adjustment unit configured to individually modify operating parameters for one or more of the plurality of separately-selectable portions in response to the comparing of respective results with the reference.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: June 27, 2017
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Niles Yang, Jiahui Yuan, James Fitzpatrick
  • Apparatuses and methods for voltage buffering
    Patent number: 9692398
    Abstract: An apparatuses and methods for buffering a voltage from a circuit without current drive ability are described. An example apparatus includes a voltage buffer that includes two identical stages. The first stage is configured to receive an input voltage and produce an intermediate voltage as an output. The second stage is configured to receive the intermediate voltage and provide an output voltage that is equal to the input voltage. The voltage buffer may be coupled to a current source. The second stage of the voltage buffer may have current drive ability.
    Type: Grant
    Filed: August 25, 2014
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Wei Lu Chu
  • Memory programming methods and memory systems
    Patent number: 9691441
    Abstract: Memory programming methods and memory systems are described. One example memory programming method includes programming a plurality of main cells of a main memory and erasing a plurality of second main cells of the main memory. The memory programming method further includes first re-writing one-time programmed data within a plurality of first one-time programmed cells of a one-time programmed memory during the programming and second re-writing one-time programmed data within a plurality of second one-time programmed cells of a one-time programmed memory during the erasing. Additional method and apparatus are described.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Takafumi Kunihiro
  • Circuit structure for suppressing electromagnetic interference of DDR SDRAM signals
    Patent number: 9691439
    Abstract: A circuit structure for suppressing electromagnetic interference (EMI) of DDR SDRAM signals, applied to a memory interface unit (MIU) of a DDR SDRAM, includes: a first conducting line, coupled to a reference level; a second conducting line, parallel to the first conducting line, coupled to the reference level; a third conducting line, between and parallel to the first and second conducting lines, transmitting a signal, the first, second and third conducting lines located on a same plane; and a connecting component, having two ends, one of the two ends electrically connected to the first conducting line and the other of the two ends electrically connected to the second conducting line, the connecting component crossing and electrically insulated from the third conducting line.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 27, 2017
    Assignee: MStar Semiconductor, Inc.
    Inventors: Yuan-De Jian, Ting-Kuang Wang