Patents Examined by Richard T. Elms
  • Patent number: 7502246
    Abstract: A ballistic memory cell structure employing ballistic transistor technology for switching between a read state and a store state is disclosed. The memory cell structure includes substrate structures forming a side wall and a main chamber for defining a linear ballistic channel between the two. The main chamber is formed to include a deflection channel with deflective surfaces to deflect an electron emitted from an electron source into the memory cell structure. Deflection controllers are coupled to the substrate structures for generating biasing fields that adjust the trajectory of electrons flowing through the linear ballistic channel and the deflection channel. Logic output terminals are positioned beyond channel exits for registering exiting electrons and determining a read or store state.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: March 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: David Daniel Chudy, Michael G. Lisanke, Cristian Medina
  • Patent number: 7443009
    Abstract: A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second conductivity and extend down to the buried layer. The isolated region has implanted source lines and is further subdivided by overlay strips of the second conductivity that extend substantially down to the buried layer. Each isolation region can contain one or more blocks of memory cells.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: October 28, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7443000
    Abstract: A semiconductor device includes (i) a semiconductor layer, (ii) a first insulating film formed in the semiconductor layer, (iii) a conductive film continuously formed on the semiconductor layer and the first insulation film in a line shape, (iv) a second insulating film formed between the conductive film and the semiconductor layer along the conductive film, (v) a sidewall portion which is formed on a sidewall of the conductive film along the conductive film and which includes an oxide film and a first nitride film that is formed above the semiconductor layer and separated from a region above the first insulating film through the oxide film, (vi) and impurity diffusion regions formed on a surface of the semiconductor layer on both sides of the sidewall portion.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: October 28, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hirotaka Mori
  • Patent number: 7443718
    Abstract: A magnetic memory device comprises a magnetic tunnel junction (MTJ) having a ferromagnetic free layer, and exhibits a first, relatively high resistance state, and a second, relatively low resistance state. To write to the magnetic memory device a current IMTJ is driven through the MTJ. For a first duration, the current is equal to a DC threshold current, being the DC current required to switch the multilayer structure between the first state and the second state. This induces a C-like domain structure in the free layer. For a second duration, the current IMTJ is larger than the DC threshold current. This causes the MTJ to switch states. The current requited to cause switching is less than that required using a uniform current pulse.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: October 28, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenchi Ito, Hiromasa Takahashi, Takayuki Kawahara, Riichiro Takemura
  • Patent number: 7439562
    Abstract: The present invention concerns a method for modyfing at least an electronic property of a carbon nanotube or nanowire comprising exposing said nanotube or nanowire to an acid having the formula (I) wherein R1, R2 and R3 are chosen in the group comprising (H, F, Cl, Br, I) with at least one of R1, R2 and R3 being different from H. At least part of the nanotube or nanowire may be a channel region of a field effect transistor.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: October 21, 2008
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stéphane Auvray, Jean-Philippe Bourgoin, Vincent Derycke, Marcelo Goffman
  • Patent number: 7440303
    Abstract: A semiconductor memory device includes resistance memory elements that are coupled to selection transistors addressed by word lines and bit lines. The memory elements are read by read/write lines arranged parallel to the word lines. Two successive memory elements along a read/write line are coupled to selection transistors that are coupled to different word lines.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: October 21, 2008
    Assignee: Qimonda AG
    Inventor: Corvin Liaw
  • Patent number: 7440328
    Abstract: A method of reducing gate disturb in a charge-trapping layer memory cell by applying different Vpass voltages to different sides of a selected wordline. A higher Vpass voltage is used to pass higher source/drain voltage and a lower Vpass voltage is used to pass a lower source/drain voltage. By controlling the Vpass voltages on different sides of a selected wordline, it is possible to reduce a vertical field that is established in a gate region when the Vpass voltages are applied. A reduced vertical field results in suppressed gate disturb. The method also includes a novel bit-line biasing scheme that may further reduce the vertical field and thereby may further suppress gate disturb, particularly in an array of memory cells.
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: October 21, 2008
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Yi Ying Liao, Chih Chieh Yeh, Wen Jer Tsai
  • Patent number: 7436694
    Abstract: Nonvolatile memory cell, having a first resistor that is electrically programmable in a nonvolatile fashion, a second resistor that is electrically programmable in a nonvolatile fashion, a first leakage current reducing element connected between the first resistor and an operating potential, and a second leakage current reducing element connected between the second resistor and the operating potential.
    Type: Grant
    Filed: May 31, 2006
    Date of Patent: October 14, 2008
    Assignee: Infineon Technologies AG
    Inventors: Joerg Berthold, Dieter Draxelmayr, Winfried Kamp, Michael Kund, Tim Schoenauer
  • Patent number: 7436733
    Abstract: Shifts in the apparent charge stored on a floating gate (or other charge storing element) of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates (or other adjacent charge storing elements). The problem occurs most pronouncedly between sets of adjacent memory cells that have been programmed at different times. To account for this coupling, the read process for a particular memory cell will provide compensation to an adjacent memory cell in order to reduce the coupling effect that the adjacent memory cell has on the particular memory cell.
    Type: Grant
    Filed: March 17, 2006
    Date of Patent: October 14, 2008
    Assignee: SanDisk Corporation
    Inventor: Nima Mokhlesi
  • Patent number: 7436043
    Abstract: A semiconductor device includes multiple low voltage N-well (LVNW) areas biased at different potentials and isolated from a substrate by a common N+ buried layer (NBL) and at least one high voltage N-well (HVNW) area. The LVNW areas are coupled to the common, subjacent NBL through a common P+ buried layer (PBL). The method for forming the substrate usable in a semiconductor device includes forming the NBL in a designated low voltage area of a negatively biased P-type semiconductor substrate, forming the PBL in a section of the NBL area by implanting P-type impurity ions such as indium into the PBL, and growing a P-type epitaxial layer over the PBL using conditions that cause the P-type impurity ions to diffuse into the P-type epitaxial layer such that the PBL extends into the NBL. Low-voltage P-well areas are also formed in the P-type epitaxial layer and contact the PBL.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 14, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Tzu-Chiang Sung, Chih Po Huang, Rann Shyan Yeh, Jun Xiu Liu, Chi-Hsuen Chang, Chung-I Chen
  • Patent number: 7436731
    Abstract: As operations of an SRAM, there are writing and reading operations, and only a portion of the whole memory operates during performing these operations, while another portion thereof stores a value. By lowering a current consumed in a period of storing this value, a semiconductor device with low power consumption is provided. The present invention provides a semiconductor device with reduced drive voltage in a period of storing a value, compared with a period of writing a value or a period of reading a value. Such a semiconductor device includes a power supply control circuit including an OR circuit electrically connected to a word line, an inverter circuit electrically connected to the OR circuit, and a transistor electrically connected to the OR circuit and the inverter circuit.
    Type: Grant
    Filed: July 25, 2006
    Date of Patent: October 14, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Syusuke Iwata
  • Patent number: 7436702
    Abstract: A method protects against a global data erasure an integrated circuit comprising an electrically programmable data memory and a control unit to execute commands for reading or writing in the memory. The method includes the steps of providing, in the integrated circuit, electrically programmable reference memory cells, at putting the integrated circuit into service, storing, in the reference memory cells, bits of determined value forming an authorized combination of bits and, during the operation of the integrated circuit following its putting into service, reading and evaluating the reference memory cells and blocking the integrated circuit if the reference memory cells contain a forbidden combination of bits different from the authorized combination.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: October 14, 2008
    Assignee: STMicroelectronics S.A.
    Inventors: David Naura, Christophe Moreaux, Ahmed Kari, Pierre Rizzo
  • Patent number: 7432560
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) includes a body pattern of a first conductivity type disposed on an insulating layer. A gate electrode is disposed on the body pattern. A drain region of a second conductivity type is disposed on the insulating layer and having a sidewall in contact with a first sidewall of the body pattern. An impurity-doped region of the first conductivity type is disposed on the insulating layer and having a sidewall in contact with a second sidewall of the body pattern. The MOSFET further includes a source region of the second conductivity type disposed on the impurity-doped region and having a sidewall in contact with the second sidewall of the body pattern, and a contact plug extending through the source region to contact the impurity-doped region.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoon Lim, Soon-Moon Jung, Won-Seok Cho, Jae-Hun Jeong
  • Patent number: 7433255
    Abstract: The invention relates to an information carrier, and a system for positioning such an information carrier in an apparatus. This system comprises an optical element (102) for generating a periodic array of light spots (103) intended to be applied to an information carrier (101), said information carrier (101) comprising a first periodic structure (108) intended to interfere with said periodic array of light spots (103) for generating a first Moiré pattern, and a second periodic structure (109) intended to interfere with said periodic array of light spots (103) for generating a second Moiré pattern, analysis means for deriving from said first and second Moiré patterns, the angle value (S) between said periodic array of light spots (103) and said information carrier (101), and actuation means (AC1-AC2-AC3) for adjusting the angular position of said information carrier (101) with respect to said array of light spots (103), from control signals (114) derived based on said angle value (S).
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 7, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Robert Frans Maria Hendriks, Thomas Jan De Hoog, Peter Van Der Walle
  • Patent number: 7433227
    Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a chalcogenide glass region is provided with a plurality of alternating tin chalcogenide and metal layers proximate thereto. The method of forming the device comprises sputtering the alternating tin chalcogenide and metal layers.
    Type: Grant
    Filed: August 17, 2007
    Date of Patent: October 7, 2008
    Assignee: Micron Technolohy, Inc.
    Inventors: Kristy A. Campbell, Jon Daley, Joseph F. Brooks
  • Patent number: 7433219
    Abstract: A semiconductor device includes a CAM cell array that stores the operation setting information as to the semiconductor device, a controller that controls read and write of the CAM cell array, a row decoder, and a column decoder. With this structure, different row addresses are allocated to respective functions of the operation setting information. Accordingly, stress is not caused in the CAM cell array of the unselected functions at the time of programming.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: October 7, 2008
    Assignee: Spansion LLC
    Inventors: Shozo Kawabata, Kenji Shibata, Takaaki Furuyama, Satoru Kawamoto
  • Patent number: 7433256
    Abstract: The invention relates to an information carrier (101) intended to be read and/or written by a periodic array of light spots, said information carrier (101) comprising a data area (105) defined by a set of elementary data areas, a first periodic structure (108) intended to interfere with said periodic array of light spots for generating a first moiré pattern, a second periodic structure (109) intended to interfere with said periodic array of light spots for generating a second moiré pattern, said second periodic structure (109) being arranged perpendicularly to said first periodic structure (108). The invention also relates to an apparatus for reading and/or writing said information carrier (101).
    Type: Grant
    Filed: April 21, 2005
    Date of Patent: October 7, 2008
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Thomas Jan De Hoog, Robert Frans Maria Hendriks, Aukje Arianne Annette Kastelijn, Peter Van Der Walle
  • Patent number: 7432552
    Abstract: A body biasing structure of devices connected in series on an SOI substrate is provided. According to some embodiments, the shallow junction of common source/drain regions enables all devices to bias by only one body contact on an SOI substrate like a conventional bulk MOSFET, and the floating body effect on an SOI substrate can be prevented.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 7, 2008
    Assignees: Seoul National University Industry Foundation, Samsung Electronics Co., Ltd.
    Inventors: Byung-Gook Park, Tae-Hoon Kim, II-Han Park
  • Patent number: RE41351
    Abstract: A CAM array including volatile or non-volatile ternary CAM cells that discharge their associated match line through a special discharge line (e.g., a low match line), instead of through the bit line, is disclosed. Each ternary CAM cell includes a pair of storage elements that are used to store a data bit value, a comparison element that is used to compare the stored value with an applied data value, and a discharge element that is coupled between the discharge line and the match line. During operation, when the applied data value matches the stored value, the discharge element de-couples the discharge line from the match line (i.e., a high voltage on the match line remains high). Conversely, when the applied data value does not match the stored value, the discharge elements couple the discharge line to the match line, thereby discharging the match line to the discharge line.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: May 25, 2010
    Assignee: NetLogic Microsystems, Inc.
    Inventors: Chuen-Der Lien, Chau-Chin Wu
  • Patent number: RE41734
    Abstract: A read-only memory having a multiplicity of memory cells whose contents can be read out with appropriate addressing by word, bit and source lines. The read-only memory is distinguished by the fact that the memory cells which can be addressed via an individual word line are divided into a multiplicity of groups, to each of which a separate common source line is assigned. Accordingly, a group-by-group read-out of the memory cells which can be addressed via an individual word line is carried out.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: September 21, 2010
    Assignee: Infineon Technologies AG
    Inventor: Holger Sedlak