Patents Examined by Richard T. Elms
  • Patent number: 7403407
    Abstract: A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: July 22, 2008
    Assignee: Netlogic Microsystems, Inc.
    Inventor: Sanjay M. Wanzakhade
  • Patent number: 7403437
    Abstract: The present invention provides a ROM test circuit capable of shortening a test time and a test method therefor. When data written into a plurality of ROMs are tested, data of the ROM(1) and ROM(2) are selected based on the output data of the specific ROM(3). Then, the selected data are compared with expected values to thereby perform testing thereof. Therefore, the contents of the ROM(3) are also tested within the time required to test each of the ROM(1) and ROM(2), thus making it possible to shorten a test time.
    Type: Grant
    Filed: April 18, 2005
    Date of Patent: July 22, 2008
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Kenichi Handa
  • Patent number: 7403431
    Abstract: A method of reading a flash memory device wherein the status of a predetermined cell is read in such a way that a plurality of page buffers connected to a memory cell array through a plurality of bit lines are divided into at least two group, and the page buffers are sequentially driven on a group basis. A power loss problem caused by excessive current consumption occurring since all page buffers operate at the same time is avoided.
    Type: Grant
    Filed: April 11, 2005
    Date of Patent: July 22, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Duck Ju Kim
  • Patent number: 7403424
    Abstract: A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: July 22, 2008
    Assignee: SanDisk Corporation
    Inventors: Gerrit Jan Hemink, Teruhiko Kamei
  • Patent number: 7403443
    Abstract: A semiconductor memory device is disclosed having a layout including, alternating pluralities of memory cell arrays and word line driving blocks arranged next to alternating pluralities of sense amplifier blocks and conjunction blocks, such that each sense amplifier block is located lateral to a corresponding memory cell array, and each conjunction block is located lateral to a corresponding word line driving block. Each sense amplifier block alternately includes one of a supply voltage driver and a ground voltage driver.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: July 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-hwa Lee, Hong-jun Lee
  • Patent number: 7403408
    Abstract: A semiconductor memory device that satisfies needs of both a large number of memory banks and a higher operation speed is provided. A semiconductor memory device includes a plurality of data terminal pads, and a plurality of memory banks independently subject to memory access. Each of the memory banks is divided into a plurality of submemory banks. The data terminal pads are also divided into a plurality of groups so as to be associated with submemory banks obtained by the division. Blocks each including submemory banks obtained by the division and data terminal pads associated with the submemory banks are arranged so as not to overlap each other on a semiconductor chip.
    Type: Grant
    Filed: May 23, 2005
    Date of Patent: July 22, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Otori, Masatoshi Hasegawa, Mitsugu Kusunoki, Masatoshi Sakamoto
  • Patent number: 7400541
    Abstract: A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal based on the number of changed bits by comparing respective bit signals of the input data signal and a previous input data signal. The comparison deciding unit generates an inversion control signal which controls whether the input data will be inverted or not. In a second mode, the comparison deciding unit generates an inversion control signal based on the predominant logic state of the input data signal bits. A data converting unit is configured to invert the input data signal in response to the inversion control signal. Method embodiments are also disclosed.
    Type: Grant
    Filed: September 28, 2007
    Date of Patent: July 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Jin Jang, Jeong-Don Lim
  • Patent number: 7400520
    Abstract: In one embodiment, a CAM is provided that includes; a plurality of memory cells grouped to store a word, wherein the memory cells are organized into a plurality of ripple groups, each ripple group including a complex logic gate configured to determine whether a stored content for the ripple group's memory cells matches a corresponding portion of a comparand word if an enable input for the ripple group is asserted, each complex logic gate asserting an output if the determination indicates a match, the ripple groups being arranged from a first ripple group to a last ripple group such that the output from the first ripple group's complex logic gate functions as the enable input for a second ripple group's complex logic gate and so on such that an output from a next-to-last ripple group's complex logic gate functions as the enable input for the last ripple group's complex logic gate.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: July 15, 2008
    Assignee: Norvelics, LLC
    Inventors: Gil I. Winograd, Esin Terzioglu, Morteza Cyrus Afghahi
  • Patent number: 7400539
    Abstract: A device includes a number of terminals for transferring input data and output data to and from a memory array. The memory device includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information or time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: July 15, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joo S. Choi
  • Patent number: 7400534
    Abstract: A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically connected between the odd-numbered bit lines and the cell source lines and belonging to the same rows as the first memory elements. A potential corresponding to data to be programmed is applied to the first memory element via the even-numbered bit line and a potential which suppresses programming is applied to the second memory element via the cell source line while the odd-numbered bit lines are kept in an electrically floating state when data is programmed into the first memory element.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Patent number: 7400528
    Abstract: Methods and devices for programming conductive bridging RAM (CBRAM) memory cells improve the cycle stability by ensuring that the memory cells are erased before being written to anew. Optionally, in the event of overwriting the memory cells, memory cells may be written to only when the writing operation would alter the cell content (i.e., the state of bit stored in the memory cell is being changed from a logical 0 to a logical 1 or vice versa).
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: July 15, 2008
    Assignee: Qimonda AG
    Inventors: Thomas Happ, Michael Kund
  • Patent number: 7397692
    Abstract: An SRAM cell. The SRAM cell includes a first CMOS inverter and a second CMOS inverter, an input of the first inverter connected to an output of the second inverter and an input of the second inverter connected to an output of the first inverter, a first MOSFET interposed between an output of the first CMOS inverter and a first plate of a first capacitor, a second plate of the first capacitor connected to a high voltage terminal of a power supply; a second MOSFET interposed between an output of the second CMOS inverter and a first plate of a second capacitor, a second plate of the second capacitor connected to the high voltage terminal of the power supply; and a control signal line connected to a gate of the first MOSFET and a gate of the second MOSFET.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: July 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ethan Harrison Cannon, Toshiharu Furukawa, David Vaclav Horak, Charles William Koburger, III, Jack A. Mandelman
  • Patent number: 7397712
    Abstract: Some embodiments of the invention include a memory device having a number of data terminals for transferring data signals and a number of strobe terminals for transferring strobe signals representing timing information of the data. The strobe terminals have a fixed signal level in an inactive mode of the memory device. The memory further includes a controller for reducing signal instability of the strobe signals when the memory device switches from the inactive mode to a data transfer mode. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 8, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Joo S Choi, Yogesh Sharma
  • Patent number: 7397690
    Abstract: Discussed are models and methods to create stable binary and non-binary sequential devices including one or more logic functions of which an output signal is uniquely related to an input signal. Methods and apparatus for non-binary single independent input information retaining devices from two logic functions are discussed. Memory elements using the information retaining devices and methods are also discussed. Methods and apparatus for n-valued memory devices including n-valued inverters with feedback are discussed. Binary and non-binary information retaining elements with two logic functions and two independent inputs are discussed. Also discussed are n-valued gating devices that can be combined with n-valued information retaining devices to form n-valued memory devices. Methods and apparatus for single non-binary n-valued logic function latches are discussed. Single non-binary n-valued function methods realizing (n?1)-valued latching methods controlled by an nth state are also discussed.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: July 8, 2008
    Assignee: Temarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 7397683
    Abstract: When one or more storage data are coincident with single search data (12), an associative memory (1) carries out logical sum for all of storage data with a valid state for storage data as true. The result of logical sum is used as matched data logical-OR information. In a primary searching operation, the associative memory (1) is supplied with the search data (12) to provide the matched data logical-OR information on matched data logical-OR lines. Then, the associative memory (1) carries out a secondary searching operation supplied as search data with the matched data logical-OR information obtained by all of storage data coincident upon the primary searching operation. Only a match line (5) coincident with the matched data logical-OR information is selected as the secondary search result. The associative memory is used in a network router to calculate an optimum memory address signal (403) by encoding the selected match line (5).
    Type: Grant
    Filed: February 21, 2007
    Date of Patent: July 8, 2008
    Assignee: Terminus Technology Limited
    Inventor: Naoyuki Ogura
  • Patent number: 7397684
    Abstract: A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: July 8, 2008
    Assignee: Infineon Technologies, AG
    Inventors: Hermann Ruckerbauer, Ralf Schledz, Johannes Stecker, Dominique Savignac, Georg Braun
  • Patent number: 7397700
    Abstract: A non-volatile memory electronic device is integrated on a semiconductor and is of the Flash EEPROM type with an architecture of the NAND type including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells and with at least one associated row decoding circuit portion. Advantageously, the matrix includes at least one logic sector with pairs of rows or word lines being short-circuited with each other and referring to a respective biasing terminal, one for each pair, and in that the row decoding circuit portion includes a single select block which controls a single multiplexer for the logic sector for the regulation of the signals applied to the biasing terminals.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: July 8, 2008
    Assignee: STMicroelectronics S.r.l.
    Inventors: Luigi Pascucci, Paolo Rolandi
  • Patent number: 7394686
    Abstract: A semiconductor storage cell includes first and second source/drain regions underlying first and second trenches defined in a semiconductor substrate. Sidewalls of the trenches are lined with a charge storage stack that includes a layer of discontinuous storage elements (DSEs), which are preferably silicon nanocrystals. Spacer control gates are located in the trenches adjacent to the charge storage stacks on the trench sidewalls. The trench depth exceeds the spacer height so that a gap exists between a top of the spacers and the top of the substrate. A continuous select gate layer overlies the first trench. The gap facilitates ballistic programming of the DSEs adjacent to the gap by accelerating electrons traveling substantially perpendicular to the trench sidewalls. The storage cell may employ hot carrier injection programming to program a portion of the DSEs proximal to the source/drain regions.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: July 1, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Craig T. Swift, Gowrishankar L. Chindalore
  • Patent number: 7394687
    Abstract: A non-volatile memory cell includes a volatile storage device that stores a corresponding logic state in response to electrical stimulus; and a shadow memory device coupled to the volatile storage device. The shadow memory device receives and stores the corresponding logic state in response to electrical stimulus. The shadow memory device includes a non-volatile nanotube switch that stores the corresponding state of the shadow device.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: July 1, 2008
    Assignee: Nantero, Inc.
    Inventors: Claude L. Bertin, Frank Guo, Thomas Ruckes, Steven L. Konsek, Mitchell Meinhold, Max Strasburg, Ramesh Sivarajan, X. M. H. Huang
  • Patent number: 7394718
    Abstract: There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate it relying on the specific rule. The present invention proposes a scheme that classifies data transmission units corresponding to each bank into plural groups, each group having some continuous data transmission units, and makes bus lines of the global data bus to be arranged alternately for each group. In other words, the global data bus line arrangement scheme suggested by the present invention may be defined as grouped alternate arrangement scheme. In this case, the overlap interval between adjacent global data bus lines can be reduced largely and skew problem by lines can also be solved.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: July 1, 2008
    Assignee: Hynix Semiconductor, Inc.
    Inventors: Kyoung-Nam Kim, Seok-Cheol Yoon