Patents Examined by Richard T. Elms
  • Patent number: 7391074
    Abstract: A non-volatile memory transistor with a nanocrystal-containing floating gate formed by nanowires is disclosed. The nanocrystals are formed by the growth of short nanowires over a crystalline program oxide. As a result, the nanocrystals are single-crystals of uniform size and single-crystal orientation.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventor: Guy M. Cohen
  • Patent number: 7391642
    Abstract: A method for programming a phase change memory cell is discussed. A phase change memory cell includes a memory element of a phase change material having a first state, in which the phase change material is crystalline and has a minimum resistance level, a second state in which the phase change material is amorphous and has a maximum resistance level, and a plurality of intermediate states, in which the phase change material includes both crystalline regions and amorphous regions and has intermediate resistance levels. According to the method, a plurality of programming pulses are provided to the phase change memory cell; programming energies respectively associated to the programming pulses are lower than a threshold energy which is required to bring the phase change material to the second state.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: June 24, 2008
    Assignee: Intel Corporation
    Inventors: George Gordon, Stephen Hudgens, Fabio Pellizzer, Agostino Pirovano
  • Patent number: 7391633
    Abstract: A sensing circuit for use with a CAM circuit including multiple match lines and multiple CAM cells connected to the match lines includes at least one charge sharing circuit and at least one switching circuit connected to the charge sharing circuit. The switching circuit is operative to selectively connect the charge sharing circuit to a corresponding one of the match lines as a function of a first control signal supplied to the switching circuit. The sensing circuit further includes at least one comparator circuit connected to the corresponding match line and operative to generate an output signal indicative of a match between search data supplied to at least a given one of the CAM cells connected to the corresponding match line and data stored in the given CAM cell. The charge sharing circuit is operative to remove an amount of charge on the corresponding match line so as to reduce a voltage on the corresponding match line in conjunction with a search operation of the CAM cell.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: June 24, 2008
    Assignee: Agere Systems Inc.
    Inventors: Dennis E. Dudeck, Donald Albert Evans, Hai Quang Pham, Wayne E. Werner, Ronald James Wozniak
  • Patent number: 7388799
    Abstract: A semiconductor memory device for consuming a uniform amount of current includes a memory cell block including a N normal wordline and a M preliminary wordline; a refresh address counting block for outputting a refresh address, having a plurality of bits, corresponding to the N normal wordline and the M preliminary wordline; a refresh counting control block for resetting the refresh address counting block when the refresh address counts a predetermined count during a test mode; and a row decoding block for refreshing unit cells coupled to the N normal wordline and unit cells coupled to the M preliminary wordline of the memory cell block according to the refresh address and a redundancy control signal outputted from the refresh counting control block, wherein M, N are positive integers.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: June 17, 2008
    Assignee: Hynix Semiconductor Inc.
    Inventor: Yong-Bok An
  • Patent number: 7388805
    Abstract: A delay locked loop (DLL) circuit for a synchronous semiconductor memory device which can control a delay time of a feedback loop within the DLL circuit according to the magnitude of an external load, and a method of generating information about a load connected to a data pin of a synchronous semiconductor memory device are provided.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jun Lee, Hoe-Ju Chung
  • Patent number: 7382664
    Abstract: A nonvolatile memory array includes a grid of word lines WL1, . . . ,WL6 and bit lines BL1, . . . ,BL8. Of a plurality of memory cells 210, each memory cell is located at an intersection region of one of the word lines and one of the bit lines. A read/write circuit 280 for reading/writing a data word including a plurality of bits is operative to map each pair of sequential bits of the data word to a respective pair of memory cells located at intersection regions of both a different word line and a different bit line.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: June 3, 2008
    Assignee: NXP B.V.
    Inventor: Kim Le Phan
  • Patent number: 7382648
    Abstract: A nanomechanical device includes a nanostructure, such as a MWNT, located between two electrodes. The device switches from an OFF state to an ON state by extension of at least one inner shell of the nanostructure relative to at least one outer shell of the nanostructure upon an application of a voltage between the electrodes. If desired, the device may also switch from the ON state to the OFF state upon an application of a gate voltage to a gate electrode located adjacent to the nanostructure.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: June 3, 2008
    Assignee: California Institute of Technology
    Inventor: Marc William Bockrath
  • Patent number: 7382649
    Abstract: A nonvolatile semiconductor memory includes memory cell units, each having memory cell transistors aligned in a column direction and capable of writing and erasing electronic data; and contacts on active areas, arranged on both sides of memory cell unit arrays in which the memory cell units are serially connected in the column direction, and the contacts on active areas are shared by the memory cell unit arrays; wherein, the respective memory cell unit arrays are located having a periodical shift length equal to and or more than the integral multiple length of the periodical length of the memory cell units aligned in the column direction so as to be staggered from each other as compared with neighboring memory cell unit arrays aligned in the row direction.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: June 3, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuhiko Matsunaga, Fumitaka Arai, Makoto Sakuma, Tadashi Iguchi, Hisashi Watanobe, Hiroaki Tsunoda
  • Patent number: 7382643
    Abstract: The magnetoresistive effect element comprises a pinned magnetic layer 16 having a multilayered synthetic antiferromagnet (SAF) structure, a nonmagnetic spacer layer 18 formed on the pinned magnetic layer 16, a free magnetic layer 20 formed on the nonmagnetic spacer layer 18 and formed of a single ferromagnetic layer, a nonmagnetic spacer layer 22 formed on the free magnetic layer 20, and a pinned magnetic layer 24 of a multilayered SAF structure formed on the nonmagnetic spacer layer 22, wherein a magnetization direction of the ferromagnetic layer 16c of the pinned magnetic layer 16, which is nearest the free magnetic layer 20, and a magnetization direction of the ferromagnetic layer 24a of the pinned magnetic layer 24, which is nearest the free magnetic layer 20, are opposite to each other.
    Type: Grant
    Filed: January 25, 2006
    Date of Patent: June 3, 2008
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Ashida, Masashige Sato, Shinjiro Umehara, Kazuo Kobayashi
  • Patent number: 7382673
    Abstract: A memory includes a column segment including memory cells along word lines, and a parity generation circuit configured to receive a first serial data stream of data bit values stored in memory cells along a word line and determine a first parity value of the first serial data stream upon entry of self refresh.
    Type: Grant
    Filed: June 15, 2005
    Date of Patent: June 3, 2008
    Assignee: Infineon Technologies AG
    Inventor: Klaus Hummler
  • Patent number: 7379375
    Abstract: Memory circuits having different configurations of local word line driving circuits (LWLDC) and methods for designing such circuits are provided. The memory circuits include an array of memory cells and a plurality of local word lines each coupled to a different subset of the array of memory cells. The memory circuit further includes a plurality of LWLDC respectively coupled to the plurality of local word lines, a global word line bus coupled to the plurality of LWLDC, and a global word line driving circuit (GWLDC) coupled to the global word line bus. At least one of the plurality of LWLDC may be configured to have a smaller amount of load capacitance than another LWLDC arranged comparatively farther from the GWLDC. In some embodiments, the variance of load capacitance may be induced by a variance of size among the plurality of LWLDC, specifically with reference to different transistor width dimensions.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: May 27, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventor: Tao Peng
  • Patent number: 7379343
    Abstract: Shifts in the apparent charge stored on a floating gate of a non-volatile memory cell can occur because of coupling of an electric field based on the charge stored in adjacent floating gates. The shift in apparent charge can lead to erroneous readings by raising the apparent threshold voltage, and consequently, lowering the sensed conduction current of a memory cell. The read process for a selected memory cell takes into account the state of one or more adjacent memory cells. If an adjacent memory cell is in one or more of a predetermined set of programmed states, a compensation current can be provided to increase the apparent conduction current of the selected memory cell. An initialization voltage is provided to the bit line of the programmed adjacent memory cell to induce a compensation current between the bit line of the programmed adjacent memory cell and the bit line of the selected memory cell.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: May 27, 2008
    Assignee: SanDisk Corporation
    Inventor: Raul-Adrian Cernea
  • Patent number: 7379361
    Abstract: A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: May 27, 2008
    Assignee: Kingston Technology Corp.
    Inventors: Ramon S. Co, David Sun
  • Patent number: 7379339
    Abstract: The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: May 27, 2008
    Assignee: Infineon Technologies AG
    Inventors: Edvin Paparisto, Stephan Rogl
  • Patent number: 7379372
    Abstract: An accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device including a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a programming unit to program the memory cells corresponding to the detected portions of the program data responsive to the scanning.
    Type: Grant
    Filed: July 13, 2005
    Date of Patent: May 27, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-Yong Jeong
  • Patent number: 7379349
    Abstract: A semiconductor device includes: a plurality of memory macros, each of which includes a plurality of memory cells, is activated in accordance with a corresponding active macro selection signal, and operates in an active mode according to a corresponding active mode control signal; and a control unit for generating and outputting, in accordance with an input operation mode control signal, the active macro selection signals and the active mode control signals that correspond to the respective memory macros, so that two or more of the memory macros are activated simultaneously.
    Type: Grant
    Filed: July 15, 2004
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kenji Motomochi
  • Patent number: 7379382
    Abstract: The timing of output signals can be controlled by coupling a digital signal through a signal distribution tree having a plurality of branches extending from an input node to respective clock inputs of a plurality of latches. A phase interpolator is included in a signal path common to all of the branches, and a respective delay line is included in each of the branches. Each of the latches couples a signal applied to its data input to an output terminal responsive to a transition of the digital signal applied to its clock input. The delay lines are adjusted so that the latches are simultaneously clocked. The delay of the phase interpolator is adjusted so that the signals are coupled to the output terminals of the latches with a predetermined timing relationship relative to signals coupled to output terminals of a second signal distribution tree.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: May 27, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Paul A. LaBerge
  • Patent number: 7376001
    Abstract: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Grant
    Filed: October 13, 2005
    Date of Patent: May 20, 2008
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Qiuyi Ye, Yuen H. Chan, Anirudh Devgan
  • Patent number: 7376012
    Abstract: A data writing method is disclosed. In a memory system comprising a NAND flash memory and a controller which controls the memory, the memory system storing data provided from a host to the NAND flash memory, the data writing method comprises a steps of specifying a column address in which a column failure which has occurred in the NAND flash memory by the controller, and a step of, during writing into the NAND flash memory, writing data of a first logic level into a memory cell which corresponds to the specified column address regardless of write data provided from the controller.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: May 20, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Kawamoto, Yoshiyuki Tanaka, Hiroshi Sukegawa
  • Patent number: 7372744
    Abstract: A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: May 13, 2008
    Assignees: Kabushiki Kaisha Toshiba, Solid State System Co., Ltd.
    Inventors: Hitoshi Shiga, Chih-Chung Chen, Chih-Hung Wang, Sheng-Lin Hung